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Searched refs:mbar2_writeLong (Results 1 – 3 of 3) sorted by relevance

/arch/m68k/cpu/mcf52x2/
A Dspeed.c49 mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ in get_clocks()
50 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ in get_clocks()
52 mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ in get_clocks()
A Dcpu_init.c206 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); in cpu_init_f()
680 mbar2_writeLong(MCFSIM_GPIO_FUNC, CFG_SYS_GPIO_FUNC); in cpu_init_f()
681 mbar2_writeLong(MCFSIM_GPIO1_FUNC, CFG_SYS_GPIO1_FUNC); in cpu_init_f()
682 mbar2_writeLong(MCFSIM_GPIO_EN, CFG_SYS_GPIO_EN); in cpu_init_f()
683 mbar2_writeLong(MCFSIM_GPIO1_EN, CFG_SYS_GPIO1_EN); in cpu_init_f()
684 mbar2_writeLong(MCFSIM_GPIO_OUT, CFG_SYS_GPIO_OUT); in cpu_init_f()
685 mbar2_writeLong(MCFSIM_GPIO1_OUT, CFG_SYS_GPIO1_OUT); in cpu_init_f()
711 mbar2_writeLong(MCFSIM_GPIO_INT_EN, 0x00000080); in cpu_init_f()
714 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); /* Enable a 1 cycle pre-drive cycle on CS1 */ in cpu_init_f()
720 mbar2_writeLong(MCFSIM_IDECONFIG1, 0x00000020); in cpu_init_f()
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/arch/m68k/include/asm/
A Dm5249.h22 #define mbar2_writeLong(x,y) *((volatile unsigned long *) (CFG_SYS_MBAR2 + x)) = y macro

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