Searched refs:mdctl (Results 1 – 7 of 7) sorted by relevance
| /arch/arm/mach-keystone/ |
| A D | psc.c | 97 u32 mdctl; in psc_set_state() local
131 mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, state); in psc_set_state()
157 u32 mdctl; in psc_enable_module() local
175 u32 mdctl; in psc_disable_module() local
181 mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0); in psc_disable_module()
201 u32 mdctl; in psc_set_reset_iso() local
205 mdctl = PSC_REG_MDCTL_SET_RESET_ISO(mdctl, 1); in psc_set_reset_iso()
257 if ((mdctl & PSC_REG_MDCTL_SET_LRSTZ(mdctl, 1))) { in psc_module_keep_in_reset_enabled()
258 mdctl = PSC_REG_MDCTL_SET_LRSTZ(mdctl, 0); in psc_module_keep_in_reset_enabled()
268 mdctl = PSC_REG_MDCTL_SET_NEXT(mdctl, next_state); in psc_module_keep_in_reset_enabled()
[all …]
|
| /arch/arm/mach-imx/ |
| A D | mmdc_size.c | 27 #define ESD_MMDC_CTL_GET_ROW(mdctl) ((mdctl >> 24) & 7) argument
28 #define ESD_MMDC_CTL_GET_COLUMN(mdctl) ((mdctl >> 20) & 7) argument
29 #define ESD_MMDC_CTL_GET_WIDTH(mdctl) ((mdctl >> 16) & 3) argument
30 #define ESD_MMDC_CTL_GET_CS1(mdctl) ((mdctl >> 30) & 1) argument
|
| /arch/arm/mach-davinci/ |
| A D | psc.c | 34 dv_reg_p mdstat, mdctl, ptstat, ptcmd; in lpsc_transition() local
42 mdctl = &psc_regs->psc0.mdctl[id]; in lpsc_transition()
49 mdctl = &psc_regs->psc1.mdctl[id]; in lpsc_transition()
60 writel((readl(mdctl) & ~PSC_MDCTL_NEXT) | state, mdctl); in lpsc_transition()
|
| /arch/arm/mach-davinci/include/mach/ |
| A D | psc_defs.h | 49 unsigned int mdctl[52]; /* 0xA00 */ member
|
| A D | hardware.h | 180 dv_reg mdctl[PSC_PSC0_MODULE_ID_CNT]; member
185 dv_reg mdctl[PSC_PSC1_MODULE_ID_CNT]; member
|
| /arch/arm/mach-imx/mx6/ |
| A D | ddr.c | 311 cs0_enable_initial = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
312 cs1_enable_initial = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
355 clrbits_le32(&mmdc0->mdctl, 1 << 30); /* clear SDE_1 */ in mmdc_do_dqs_calibration()
357 clrbits_le32(&mmdc0->mdctl, 1 << 31); /* clear SDE_0 */ in mmdc_do_dqs_calibration()
363 cs0_enable = readl(&mmdc0->mdctl) & 0x80000000; in mmdc_do_dqs_calibration()
364 cs1_enable = readl(&mmdc0->mdctl) & 0x40000000; in mmdc_do_dqs_calibration()
571 setbits_le32(&mmdc0->mdctl, 1 << 30); in mmdc_do_dqs_calibration()
575 setbits_le32(&mmdc0->mdctl, 1 << 31); in mmdc_do_dqs_calibration()
1228 mmdc0->mdctl |= (1 << 31) | /* SDE_0 for CS0 */ in mx6_lpddr2_cfg()
1521 mmdc0->mdctl = (ddr3_cfg->rowaddr - 11) << 24 | /* ROW */ in mx6_ddr3_cfg()
[all …]
|
| /arch/arm/include/asm/arch-mx6/ |
| A D | mx6-ddr.h | 39 u32 mdctl; member
|
Completed in 19 milliseconds