Searched refs:mdiv (Results 1 – 6 of 6) sorted by relevance
| /arch/arm/mach-socfpga/ |
| A D | clock_manager_s10.c | 44 u32 mdiv, refclkdiv, mscnt, hscnt, vcocalib; in cm_basic_init() local
54 mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
58 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
59 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
81 mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & in cm_basic_init()
85 mscnt = CLKMGR_MSCNT_CONST / (CLKMGR_MDIV_CONST + mdiv) / refclkdiv; in cm_basic_init()
86 hscnt = (mdiv + CLKMGR_MDIV_CONST) * mscnt / refclkdiv - in cm_basic_init()
201 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
226 vco = vco * (CLKMGR_MDIV_CONST + mdiv); in cm_get_main_vco_clk_hz()
232 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
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| /arch/arm/mach-exynos/ |
| A D | exynos4_setup.h | 325 #define SET_PLL(mdiv, pdiv, sdiv) ((ENABLE << 31)\ argument
326 | (mdiv << 16) \
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| A D | exynos5_setup.h | 22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) argument
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| /arch/arm/include/asm/arch-imx8m/ |
| A D | clock_imx8mm.h | 18 .mdiv = (_m), \
40 int mdiv; member
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| /arch/arm/include/asm/arch-tegra/ |
| A D | bpmp_abi.h | 1364 uint16_t mdiv; /**< input divider value */ member
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| /arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mm.c | 111 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in fracpll_configure()
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