1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * From Coreboot src/southbridge/intel/bd82x6x/me.h
4 *
5 * Coreboot copies lots of code around. Here we are trying to keep the common
6 * code in a separate file to reduce code duplication and hopefully make it
7 * easier to add new platform.
8 *
9 * Copyright (C) 2016 Google, Inc
10 */
11
12 #ifndef __ASM_ME_COMMON_H
13 #define __ASM_ME_COMMON_H
14
15 #include <linux/compiler.h>
16 #include <linux/string.h>
17 #include <linux/types.h>
18 #include <pci.h>
19
20 #define MCHBAR_PEI_VERSION 0x5034
21
22 #define ME_RETRY 100000 /* 1 second */
23 #define ME_DELAY 10 /* 10 us */
24
25 /*
26 * Management Engine PCI registers
27 */
28
29 #define PCI_CPU_MEBASE_L 0x70 /* Set by MRC */
30 #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */
31
32 #define PCI_ME_HFS 0x40
33 #define ME_HFS_CWS_RESET 0
34 #define ME_HFS_CWS_INIT 1
35 #define ME_HFS_CWS_REC 2
36 #define ME_HFS_CWS_NORMAL 5
37 #define ME_HFS_CWS_WAIT 6
38 #define ME_HFS_CWS_TRANS 7
39 #define ME_HFS_CWS_INVALID 8
40 #define ME_HFS_STATE_PREBOOT 0
41 #define ME_HFS_STATE_M0_UMA 1
42 #define ME_HFS_STATE_M3 4
43 #define ME_HFS_STATE_M0 5
44 #define ME_HFS_STATE_BRINGUP 6
45 #define ME_HFS_STATE_ERROR 7
46 #define ME_HFS_ERROR_NONE 0
47 #define ME_HFS_ERROR_UNCAT 1
48 #define ME_HFS_ERROR_IMAGE 3
49 #define ME_HFS_ERROR_DEBUG 4
50 #define ME_HFS_MODE_NORMAL 0
51 #define ME_HFS_MODE_DEBUG 2
52 #define ME_HFS_MODE_DIS 3
53 #define ME_HFS_MODE_OVER_JMPR 4
54 #define ME_HFS_MODE_OVER_MEI 5
55 #define ME_HFS_BIOS_DRAM_ACK 1
56 #define ME_HFS_ACK_NO_DID 0
57 #define ME_HFS_ACK_RESET 1
58 #define ME_HFS_ACK_PWR_CYCLE 2
59 #define ME_HFS_ACK_S3 3
60 #define ME_HFS_ACK_S4 4
61 #define ME_HFS_ACK_S5 5
62 #define ME_HFS_ACK_GBL_RESET 6
63 #define ME_HFS_ACK_CONTINUE 7
64
65 struct me_hfs {
66 u32 working_state:4;
67 u32 mfg_mode:1;
68 u32 fpt_bad:1;
69 u32 operation_state:3;
70 u32 fw_init_complete:1;
71 u32 ft_bup_ld_flr:1;
72 u32 update_in_progress:1;
73 u32 error_code:4;
74 u32 operation_mode:4;
75 u32 reserved:4;
76 u32 boot_options_present:1;
77 u32 ack_data:3;
78 u32 bios_msg_ack:4;
79 } __packed;
80
81 #define PCI_ME_UMA 0x44
82
83 struct me_uma {
84 u32 size:6;
85 u32 reserved_1:10;
86 u32 valid:1;
87 u32 reserved_0:14;
88 u32 set_to_one:1;
89 } __packed;
90
91 #define PCI_ME_H_GS 0x4c
92 #define ME_INIT_DONE 1
93 #define ME_INIT_STATUS_SUCCESS 0
94 #define ME_INIT_STATUS_NOMEM 1
95 #define ME_INIT_STATUS_ERROR 2
96
97 struct me_did {
98 u32 uma_base:16;
99 u32 reserved:7;
100 u32 rapid_start:1; /* Broadwell only */
101 u32 status:4;
102 u32 init_done:4;
103 } __packed;
104
105 #define PCI_ME_GMES 0x48
106 #define ME_GMES_PHASE_ROM 0
107 #define ME_GMES_PHASE_BUP 1
108 #define ME_GMES_PHASE_UKERNEL 2
109 #define ME_GMES_PHASE_POLICY 3
110 #define ME_GMES_PHASE_MODULE 4
111 #define ME_GMES_PHASE_UNKNOWN 5
112 #define ME_GMES_PHASE_HOST 6
113
114 struct me_gmes {
115 u32 bist_in_prog:1;
116 u32 icc_prog_sts:2;
117 u32 invoke_mebx:1;
118 u32 cpu_replaced_sts:1;
119 u32 mbp_rdy:1;
120 u32 mfs_failure:1;
121 u32 warm_rst_req_for_df:1;
122 u32 cpu_replaced_valid:1;
123 u32 reserved_1:2;
124 u32 fw_upd_ipu:1;
125 u32 reserved_2:4;
126 u32 current_state:8;
127 u32 current_pmevent:4;
128 u32 progress_code:4;
129 } __packed;
130
131 #define PCI_ME_HERES 0xbc
132 #define PCI_ME_EXT_SHA1 0x00
133 #define PCI_ME_EXT_SHA256 0x02
134 #define PCI_ME_HER(x) (0xc0+(4*(x)))
135
136 struct me_heres {
137 u32 extend_reg_algorithm:4;
138 u32 reserved:26;
139 u32 extend_feature_present:1;
140 u32 extend_reg_valid:1;
141 } __packed;
142
143 /*
144 * Management Engine MEI registers
145 */
146
147 #define MEI_H_CB_WW 0x00
148 #define MEI_H_CSR 0x04
149 #define MEI_ME_CB_RW 0x08
150 #define MEI_ME_CSR_HA 0x0c
151
152 struct mei_csr {
153 u32 interrupt_enable:1;
154 u32 interrupt_status:1;
155 u32 interrupt_generate:1;
156 u32 ready:1;
157 u32 reset:1;
158 u32 reserved:3;
159 u32 buffer_read_ptr:8;
160 u32 buffer_write_ptr:8;
161 u32 buffer_depth:8;
162 } __packed;
163
164 #define MEI_ADDRESS_CORE 0x01
165 #define MEI_ADDRESS_AMT 0x02
166 #define MEI_ADDRESS_RESERVED 0x03
167 #define MEI_ADDRESS_WDT 0x04
168 #define MEI_ADDRESS_MKHI 0x07
169 #define MEI_ADDRESS_ICC 0x08
170 #define MEI_ADDRESS_THERMAL 0x09
171
172 #define MEI_HOST_ADDRESS 0
173
174 struct mei_header {
175 u32 client_address:8;
176 u32 host_address:8;
177 u32 length:9;
178 u32 reserved:6;
179 u32 is_complete:1;
180 } __packed;
181
182 #define MKHI_GROUP_ID_CBM 0x00
183 #define MKHI_GROUP_ID_FWCAPS 0x03
184 #define MKHI_GROUP_ID_MDES 0x08
185 #define MKHI_GROUP_ID_GEN 0xff
186
187 #define MKHI_GET_FW_VERSION 0x02
188 #define MKHI_END_OF_POST 0x0c
189 #define MKHI_FEATURE_OVERRIDE 0x14
190
191 /* Ivybridge only: */
192 #define MKHI_GLOBAL_RESET 0x0b
193 #define MKHI_FWCAPS_GET_RULE 0x02
194 #define MKHI_MDES_ENABLE 0x09
195
196 /* Broadwell only: */
197 #define MKHI_GLOBAL_RESET 0x0b
198 #define MKHI_FWCAPS_GET_RULE 0x02
199 #define MKHI_GROUP_ID_HMRFPO 0x05
200 #define MKHI_HMRFPO_LOCK 0x02
201 #define MKHI_HMRFPO_LOCK_NOACK 0x05
202 #define MKHI_MDES_ENABLE 0x09
203 #define MKHI_END_OF_POST_NOACK 0x1a
204
205 struct mkhi_header {
206 u32 group_id:8;
207 u32 command:7;
208 u32 is_response:1;
209 u32 reserved:8;
210 u32 result:8;
211 } __packed;
212
213 struct me_fw_version {
214 u16 code_minor;
215 u16 code_major;
216 u16 code_build_number;
217 u16 code_hot_fix;
218 u16 recovery_minor;
219 u16 recovery_major;
220 u16 recovery_build_number;
221 u16 recovery_hot_fix;
222 } __packed;
223
224 #define HECI_EOP_STATUS_SUCCESS 0x0
225 #define HECI_EOP_PERFORM_GLOBAL_RESET 0x1
226
227 #define CBM_RR_GLOBAL_RESET 0x01
228
229 #define GLOBAL_RESET_BIOS_MRC 0x01
230 #define GLOBAL_RESET_BIOS_POST 0x02
231 #define GLOBAL_RESET_MEBX 0x03
232
233 struct me_global_reset {
234 u8 request_origin;
235 u8 reset_type;
236 } __packed;
237
238 enum me_bios_path {
239 ME_NORMAL_BIOS_PATH,
240 ME_S3WAKE_BIOS_PATH,
241 ME_ERROR_BIOS_PATH,
242 ME_RECOVERY_BIOS_PATH,
243 ME_DISABLE_BIOS_PATH,
244 ME_FIRMWARE_UPDATE_BIOS_PATH,
245 };
246
247 struct __packed mefwcaps_sku {
248 u32 full_net:1;
249 u32 std_net:1;
250 u32 manageability:1;
251 u32 small_business:1;
252 u32 l3manageability:1;
253 u32 intel_at:1;
254 u32 intel_cls:1;
255 u32 reserved:3;
256 u32 intel_mpc:1;
257 u32 icc_over_clocking:1;
258 u32 pavp:1;
259 u32 reserved_1:4;
260 u32 ipv6:1;
261 u32 kvm:1;
262 u32 och:1;
263 u32 vlan:1;
264 u32 tls:1;
265 u32 reserved_4:1;
266 u32 wlan:1;
267 u32 reserved_5:8;
268 };
269
270 struct __packed tdt_state_flag {
271 u16 lock_state:1;
272 u16 authenticate_module:1;
273 u16 s3authentication:1;
274 u16 flash_wear_out:1;
275 u16 flash_variable_security:1;
276 u16 wwan3gpresent:1; /* ivybridge only */
277 u16 wwan3goob:1; /* ivybridge only */
278 u16 reserved:9;
279 };
280
281 struct __packed tdt_state_info {
282 u8 state;
283 u8 last_theft_trigger;
284 struct tdt_state_flag flags;
285 };
286
287 struct __packed mbp_rom_bist_data {
288 u16 device_id;
289 u16 fuse_test_flags;
290 u32 umchid[4];
291 };
292
293 struct __packed mbp_platform_key {
294 u32 key[8];
295 };
296
297 struct __packed mbp_header {
298 u32 mbp_size:8;
299 u32 num_entries:8;
300 u32 rsvd:16;
301 };
302
303 struct __packed mbp_item_header {
304 u32 app_id:8;
305 u32 item_id:8;
306 u32 length:8;
307 u32 rsvd:8;
308 };
309
310 struct __packed me_fwcaps {
311 u32 id;
312 u8 length;
313 struct mefwcaps_sku caps_sku;
314 u8 reserved[3];
315 };
316
317 /**
318 * intel_me_status() - Check Intel Management Engine status
319 *
320 * @me_dev: Management engine PCI device
321 */
322 void intel_me_status(struct udevice *me_dev);
323
324 /**
325 * intel_early_me_init() - Early Intel Management Engine init
326 *
327 * @me_dev: Management engine PCI device
328 * Return: 0 if OK, -ve on error
329 */
330 int intel_early_me_init(struct udevice *me_dev);
331
332 /**
333 * intel_early_me_uma_size() - Get UMA size from the Intel Management Engine
334 *
335 * @me_dev: Management engine PCI device
336 * Return: UMA size if OK, -EINVAL on error
337 */
338 int intel_early_me_uma_size(struct udevice *me_dev);
339
340 /**
341 * intel_early_me_init_done() - Complete Intel Management Engine init
342 *
343 * @dev: Northbridge device
344 * @me_dev: Management engine PCI device
345 * @status: Status result (ME_INIT_...)
346 * Return: 0 to continue to boot, -EINVAL on unknown result data, -ETIMEDOUT
347 * if ME did not respond
348 */
349 int intel_early_me_init_done(struct udevice *dev, struct udevice *me_dev,
350 uint status);
351
352 int intel_me_hsio_version(struct udevice *dev, uint16_t *version,
353 uint16_t *checksum);
354
pci_read_dword_ptr(struct udevice * me_dev,void * ptr,int offset)355 static inline void pci_read_dword_ptr(struct udevice *me_dev, void *ptr,
356 int offset)
357 {
358 u32 dword;
359
360 dm_pci_read_config32(me_dev, offset, &dword);
361 memcpy(ptr, &dword, sizeof(dword));
362 }
363
pci_write_dword_ptr(struct udevice * me_dev,void * ptr,int offset)364 static inline void pci_write_dword_ptr(struct udevice *me_dev, void *ptr,
365 int offset)
366 {
367 u32 dword = 0;
368
369 memcpy(&dword, ptr, sizeof(dword));
370 dm_pci_write_config32(me_dev, offset, dword);
371 }
372 #endif
373