Home
last modified time | relevance | path

Searched refs:membaseconfig0 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h123 unsigned membaseconfig0; member
A Ddmc_init_ddr3.c111 writel(mem->membaseconfig0, &dmc->membaseconfig0); in ddr3_mem_ctrl_init()
577 writel(val, &tzasc0->membaseconfig0); in ddr3_mem_ctrl_init()
578 writel(val, &tzasc1->membaseconfig0); in ddr3_mem_ctrl_init()
A Dclock_init_exynos5.c349 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
452 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
/arch/arm/mach-exynos/include/mach/
A Ddmc.h174 unsigned int membaseconfig0; member
424 unsigned int membaseconfig0; member

Completed in 14 milliseconds