Searched refs:memc (Results 1 – 7 of 7) sorted by relevance
| /arch/mips/mach-mtmips/ |
| A D | ddr_init.c | 77 clrbits_32(memc + MEMCTL_SDRAM_CFG1_REG, RBC_MAPPING); in mc_ddr_init()
79 writel(cfg->cfg2, memc + MEMCTL_DDR_CFG2_REG); in mc_ddr_init()
80 writel(cfg->cfg3, memc + MEMCTL_DDR_CFG3_REG); in mc_ddr_init()
81 writel(cfg->cfg4, memc + MEMCTL_DDR_CFG4_REG); in mc_ddr_init()
82 writel(dq_dly, memc + MEMCTL_DDR_DQ_DLY_REG); in mc_ddr_init()
83 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in mc_ddr_init()
85 writel(cfg->cfg0, memc + MEMCTL_DDR_CFG0_REG); in mc_ddr_init()
93 writel(val, memc + MEMCTL_DDR_CFG1_REG); in mc_ddr_init()
138 mc_ddr_init(param->memc, ¶m->cfgs[sz], param->dq_dly, in ddr1_init()
210 writel(cfg0, memc + MEMCTL_SDRAM_CFG0_REG); in mc_sdr_init()
[all …]
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| A D | ddr_cal.c | 46 writel(INIT_DQS_VAL, memc + MEMCTL_DDR_DQS_DLY_REG); in dqs_test_error()
55 writel(dqsval, memc + MEMCTL_DDR_DQS_DLY_REG); in dqs_test_error()
82 if (dqs_test_error(memc, memsize, dqsval, 3)) in dqs_find_max()
97 if (dqs_test_error(memc, memsize, dqsval, 1)) in dqs_find_min()
104 void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw) in ddr_calibrate() argument
118 ddr_cfg2_reg = readl(memc + MEMCTL_DDR_CFG2_REG); in ddr_calibrate()
122 clrbits_32(memc + MEMCTL_DDR_CFG2_REG, mask); in ddr_calibrate()
125 dlls = readl(memc + MEMCTL_DLL_DBG_REG); in ddr_calibrate()
173 test_dqs = dqs_find_min(memc, memsize, FINE_MIN_START, in ddr_calibrate()
198 writel(dqs_dly, memc + MEMCTL_DDR_DQS_DLY_REG); in ddr_calibrate()
[all …]
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| /arch/mips/mach-mtmips/include/mach/ |
| A D | ddr.h | 36 void __iomem *memc; member
54 void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
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| /arch/mips/dts/ |
| A D | mt7621.dtsi | 56 mediatek,memc = <&memc>;
75 memc: memctrl@1e005000 { label
76 compatible = "mediatek,mt7621-memc", "syscon";
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| A D | mt7628a.dtsi | 255 compatible = "ralink,mt7620a-memc";
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| /arch/mips/mach-mtmips/mt7628/ |
| A D | ddr.c | 150 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE); in mt7628_ddr_init()
171 ddr_calibrate(param.memc, param.memsize, param.bus_width); in mt7628_ddr_init()
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| /arch/mips/mach-mtmips/mt7620/ |
| A D | dram.c | 86 param.memc = ioremap_nocache(MEMCTL_BASE, MEMCTL_SIZE); in mt7620_dram_init()
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