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Searched refs:mpll_con0 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos4.c86 writel(MPLL_CON0_VAL, &clk->mpll_con0); in system_clock_init()
A Dclock_init_exynos5.c627 writel(val, &clk->mpll_con0); in exynos5250_system_clock_init()
628 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0) in exynos5250_system_clock_init()
848 writel(val, &clk->mpll_con0); in exynos5420_system_clock_init()
849 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0) in exynos5420_system_clock_init()
A Dclock.c199 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
229 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
260 r = readl(&clk->mpll_con0); in exynos5_get_pll_clk()
318 r = readl(&clk->mpll_con0); in exynos542x_get_pll_clk()
/arch/arm/mach-exynos/include/mach/
A Dclock.h189 unsigned int mpll_con0; member
392 unsigned int mpll_con0; member
575 unsigned int mpll_con0; member
1068 unsigned int mpll_con0; member

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