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Searched refs:mpll_sdiv (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h49 unsigned mpll_sdiv; member
A Dclock_init_exynos5.c145 .mpll_sdiv = 0x1,
269 .mpll_sdiv = 0x0,
372 .mpll_sdiv = 0x0,
626 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5250_system_clock_init()
847 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5420_system_clock_init()

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