| /arch/x86/lib/ |
| A D | i8259.c | 29 outb(0xff, MASTER_PIC + IMR); in i8259_init()
30 outb(0xff, SLAVE_PIC + IMR); in i8259_init()
37 outb(0x20, MASTER_PIC + ICW2); in i8259_init()
38 outb(IR2, MASTER_PIC + ICW3); in i8259_init()
39 outb(ICW4_PM, MASTER_PIC + ICW4); in i8259_init()
49 outb(0x28, SLAVE_PIC + ICW2); in i8259_init()
50 outb(0x02, SLAVE_PIC + ICW3); in i8259_init()
51 outb(ICW4_PM, SLAVE_PIC + ICW4); in i8259_init()
54 outb(OCW2_SEOI | i, SLAVE_PIC + OCW2); in i8259_init()
128 outb((u8)(int_bits & 0xff), ELCR1); in configure_irq_trigger()
[all …]
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| A D | i8254.c | 23 outb(countdown & 0xff, PIT_BASE + PIT_T2); in i8254_set_beep_freq()
24 outb((countdown >> 8) & 0xff, PIT_BASE + PIT_T2); in i8254_set_beep_freq()
34 outb(PIT_CMD_CTR1 | PIT_CMD_LOW | PIT_CMD_MODE2, in i8254_init()
36 outb(TIMER1_VALUE, PIT_BASE + PIT_T1); in i8254_init()
43 outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, in i8254_init()
56 outb(PIT_CMD_CTR2 | PIT_CMD_BOTH | PIT_CMD_MODE3, in i8254_enable_beep()
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| A D | early_cmos.c | 18 outb(addr, CMOS_IO_PORT); in cmos_read8()
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| /arch/x86/cpu/qemu/ |
| A D | dram.c | 20 outb(HIGH_RAM_ADDR, CMOS_ADDR_PORT); in qemu_get_low_memory_size()
22 outb(LOW_RAM_ADDR, CMOS_ADDR_PORT); in qemu_get_low_memory_size()
33 outb(HIGH_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
35 outb(MID_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
37 outb(LOW_HIGHRAM_ADDR, CMOS_ADDR_PORT); in qemu_get_high_memory_size()
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| /arch/x86/include/asm/ |
| A D | pnp_def.h | 38 outb(reg, port); in pnp_write_config()
39 outb(value, port + 1); in pnp_write_config()
46 outb(reg, port); in pnp_read_config()
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| A D | post.h | 44 outb %al, $POST_PORT
50 outb(code, POST_PORT); in post_code()
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| A D | io.h | 194 #define outb(val, port) _outb(val, (uintptr_t)(port)) macro
300 IO_COND(addr, outb(value, port), writeb(value, addr)); in iowrite8()
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| /arch/microblaze/include/asm/ |
| A D | io.h | 49 #define outb(x, addr) ((void)writeb(x, addr)) macro
68 #define out_8(addr, x) outb(x, addr)
73 #define outb_p(val, port) outb((val), (port))
118 outb(*p++, port); in io_outsb()
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| /arch/x86/cpu/coreboot/ |
| A D | coreboot.c | 69 outb(0xcb, 0xb2); in board_final_init()
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| /arch/xtensa/include/asm/ |
| A D | io.h | 62 #define outb(val, port) writeb((val), (u8 *)((unsigned long)(port))) macro
69 #define outb_p(val, port) outb((val), (port))
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| /arch/x86/lib/fsp1/ |
| A D | fsp_common.c | 72 outb(SYS_RST | RST_CPU, IO_PORT_RESET); in arch_fsp_init()
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| /arch/x86/cpu/intel_common/ |
| A D | cpu.c | 112 outb(0x0, IO_PORT_RESET); in cpu_set_flex_ratio_to_tdp_nominal()
113 outb(SYS_RST | RST_CPU, IO_PORT_RESET); in cpu_set_flex_ratio_to_tdp_nominal()
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| A D | car2.S | 37 outb %al, %dx
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| /arch/sh/include/asm/ |
| A D | io.h | 84 #define outb(v, p) __raw_writeb(v, p) macro
100 #define outb_p(val, port) outb((val), (port))
115 #define out_8(port, val) outb(val, port)
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| /arch/x86/cpu/ |
| A D | pci.c | 44 outb(value, PCI_REG_DATA + (offset & 3)); in pci_x86_write_config()
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| A D | cpu.c | 187 outb(val, POST_PORT); in show_boot_progress()
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| /arch/nios2/include/asm/ |
| A D | io.h | 78 #define outb(val, addr) writeb(val,addr) macro
104 while (count--) outb (*p++, port); in outsb()
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| /arch/x86/cpu/ivybridge/ |
| A D | lpc.c | 185 outb(reg8, 0x61); in pch_power_options()
198 outb(reg8, 0x70); in pch_power_options()
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| /arch/riscv/include/asm/ |
| A D | io.h | 205 #define outb(v, p) __raw_writeb(v, __io(p)) macro
326 #define outb_p(val, port) outb((val), (port))
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| /arch/arm/include/asm/ |
| A D | io.h | 328 #define outb(v,p) __raw_writeb(v,__io(p)) macro
345 #define outb_p(val,port) outb((val),(port))
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| /arch/m68k/include/asm/ |
| A D | io.h | 54 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) macro
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| /arch/powerpc/include/asm/ |
| A D | io.h | 54 #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) macro
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| /arch/sandbox/include/asm/ |
| A D | io.h | 145 #define outb(val, port) _outb(val, (uintptr_t)(port)) macro
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