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Searched refs:outl (Results 1 – 19 of 19) sorted by relevance

/arch/sh/cpu/sh4/
A Dcache.c31 outl(data, addr); in cache_wback_all()
52 outl(CCR_CACHE_ICI | ccr, CCR); in cache_control()
54 outl(CCR_CACHE_STOP, CCR); in cache_control()
56 outl(CCR_CACHE_INIT, CCR); in cache_control()
/arch/x86/cpu/broadwell/
A Dpinctrl_broadwell.c177 outl(val, &regs->config[gpio].conf_a); in broadwell_pinctrl_commit()
178 outl(pin->sense_disable << CONFB_SENSE_SHIFT, in broadwell_pinctrl_commit()
200 outl(owner_gpio[set], &regs->own[set]); in broadwell_pinctrl_commit()
201 outl(route_smi[set], &regs->gpi_route[set]); in broadwell_pinctrl_commit()
202 outl(irq_enable[set], &regs->gpi_ie[set]); in broadwell_pinctrl_commit()
203 outl(reset_rsmrst[set], &regs->rst_sel[set]); in broadwell_pinctrl_commit()
206 outl(pirq2apic, &regs->pirq_to_ioxapic); in broadwell_pinctrl_commit()
A Dpch.c137 outl(set1, ACPI_BASE_ADDRESS + GPE0_EN(GPE_31_0)); in enable_all_gpe()
138 outl(set2, ACPI_BASE_ADDRESS + GPE0_EN(GPE_63_32)); in enable_all_gpe()
139 outl(set3, ACPI_BASE_ADDRESS + GPE0_EN(GPE_94_64)); in enable_all_gpe()
140 outl(set4, ACPI_BASE_ADDRESS + GPE0_EN(GPE_STD)); in enable_all_gpe()
A Dpower_state.c34 outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in prev_sleep_state()
/arch/x86/cpu/
A Dpci.c22 outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); in pci_x86_read_config()
41 outl(PCI_CONF1_ADDRESS(PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), offset), PCI_REG_ADDR); in pci_x86_write_config()
50 outl(value, PCI_REG_DATA); in pci_x86_write_config()
A Dacpi_gpe.c48 outl(mask, priv->acpi_base + GPE0_STS(bank)); in acpi_gpe_read_and_clear()
/arch/x86/include/asm/arch-quark/
A Dquark.h213 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); in qrk_pci_read_config_dword()
229 outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR); in qrk_pci_write_config_dword()
230 outl(value, PCI_REG_DATA); in qrk_pci_write_config_dword()
/arch/microblaze/include/asm/
A Dio.h51 #define outl(x, addr) ((void)writel(x, addr)) macro
77 #define outl_p(val, port) outl((val), (port))
136 outl(*p++, port); in io_outsl()
/arch/xtensa/include/asm/
A Dio.h66 #define outl(val, port) writel((val), (u32 *)((unsigned long)(port))) macro
73 #define outl_p(val, port) outl((val), (port))
/arch/sh/include/asm/
A Dio.h86 #define outl(v, p) __raw_writel(cpu_to_le32(v), p) macro
102 #define outl_p(val, port) outl((val), (port))
117 #define out_le32(port, val) outl(val, port)
/arch/nios2/include/asm/
A Dio.h80 #define outl(val, addr) writel(val,addr) macro
115 while (count--) outl (*p++, port); in outsl()
/arch/m68k/include/asm/
A Dio.h59 #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) macro
64 #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) macro
/arch/x86/include/asm/
A Dio.h196 #define outl(val, port) _outl(val, (uintptr_t)(port)) macro
310 IO_COND(addr, outl(value, port), writel(value, addr)); in iowrite32()
/arch/powerpc/include/asm/
A Dio.h59 #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) macro
64 #define outl(val, port) out_le32((u32 *)((port)+_IO_BASE), (val)) macro
/arch/riscv/include/asm/
A Dio.h207 #define outl(v, p) __raw_writel(cpu_to_le32(v), __io(p)) macro
328 #define outl_p(val, port) outl((val), (port))
/arch/x86/cpu/baytrail/
A Dacpi.c194 outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); in chipset_clear_sleep_state()
/arch/arm/include/asm/
A Dio.h330 #define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p)) macro
347 #define outl_p(val,port) outl((val),(port))
/arch/x86/cpu/ivybridge/
A Dlpc.c227 outl(reg32, pmbase + 0x04); in pch_power_options()
/arch/sandbox/include/asm/
A Dio.h147 #define outl(val, port) _outl(val, (uintptr_t)(port)) macro

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