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Searched refs:para (Results 1 – 25 of 25) sorted by relevance

/arch/arm/mach-sunxi/
A Ddram_sun8i_a33.c43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
54 para->seq = 1; in auto_detect_dram_size()
55 para->rows = 16; in auto_detect_dram_size()
56 para->rank = 1; in auto_detect_dram_size()
57 mctl_set_cr(para); in auto_detect_dram_size()
64 para->rows = 11; in auto_detect_dram_size()
72 para->seq = 0; in auto_detect_dram_size()
232 para->cs1 = 0; in mctl_channel_init()
233 para->rank = 2; in mctl_channel_init()
360 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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A Ddram_sun8i_a83t.c41 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_set_cr()
42 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
53 para->seq = 1; in auto_detect_dram_size()
54 para->rows = 16; in auto_detect_dram_size()
55 para->rank = 1; in auto_detect_dram_size()
56 mctl_set_cr(para); in auto_detect_dram_size()
63 para->rows = 11; in auto_detect_dram_size()
71 para->seq = 0; in auto_detect_dram_size()
314 para->cs1 = 0; in mctl_channel_init()
469 return para.page_size * (para.bus_width / 8) * in sunxi_dram_init()
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A Ddram_suniv.c137 ((para->sdr_ddr ? (para->bwidth >> 4) : (para->bwidth >> 5)) << 13) | in dram_para_setup()
266 dram_para_setup(para); in dram_get_dram_size()
284 dram_para_setup(para); in dram_get_dram_size()
308 para->size = 16; in dram_get_dram_size()
310 para->size = 64; in dram_get_dram_size()
312 para->size = 32; in dram_get_dram_size()
314 para->access_mode = 0; in dram_get_dram_size()
315 dram_para_setup(para); in dram_get_dram_size()
359 if (para->clk >= 144 && para->clk <= 180) in do_dram_init()
361 if (para->clk >= 180) in do_dram_init()
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A Ddram_sun9i.c349 | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank), in mctl_com_init()
384 const u32 tRTP = MAX(para->tRTP.ck, PS2CYCLES_ROUNDUP(para->tRTP.ps)); in mctl_channel_init()
385 const u32 tWTR = MAX(para->tWTR.ck, PS2CYCLES_ROUNDUP(para->tWTR.ps)); in mctl_channel_init()
387 const u32 tMRD = para->tMRD; in mctl_channel_init()
388 const u32 tMOD = MAX(para->tMOD.ck, PS2CYCLES_ROUNDUP(para->tMOD.ps)); in mctl_channel_init()
389 const u32 tCCD = para->tCCD; in mctl_channel_init()
390 const u32 tRRD = MAX(para->tRRD.ck, PS2CYCLES_ROUNDUP(para->tRRD.ps)); in mctl_channel_init()
406 const u32 tXP = MAX(para->tXP.ck, PS2CYCLES_ROUNDUP(para->tXP.ps)); in mctl_channel_init()
409 const u32 tCKE = MAX(para->tCKE.ck, PS2CYCLES_ROUNDUP(para->tCKE.ps)); in mctl_channel_init()
415 const u32 tXS = MAX(para->tXS.ck, PS2CYCLES_ROUNDUP(para->tXS.ps)); in mctl_channel_init()
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A Ddram_sun50i_h616.c286 val_lo = para->dx_dri; in mctl_phy_configure_odt()
287 val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0x04040404 : para->dx_dri; in mctl_phy_configure_odt()
297 val_lo = para->ca_dri; in mctl_phy_configure_odt()
298 val_hi = para->ca_dri; in mctl_phy_configure_odt()
304 val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR3) ? 0 : para->dx_odt; in mctl_phy_configure_odt()
305 val_hi = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt; in mctl_phy_configure_odt()
848 switch (para->type) { in mctl_phy_ca_bit_delay_compensation()
923 switch (para->type) { in mctl_phy_init()
973 switch (para->type) { in mctl_phy_init()
993 switch (para->type) { in mctl_phy_init()
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A Ddram_sun50i_a133.c123 switch (para->type) { in mctl_set_odtmap()
130 if (para->clk < 400) in mctl_set_odtmap()
374 switch (para->type) { in mctl_com_init()
471 val = para->tpr2; in mctl_phy_ca_bit_delay_compensation()
489 switch (para->type) { in mctl_phy_ca_bit_delay_compensation()
555 switch (para->type) { in mctl_phy_init()
598 switch (para->type) { in mctl_phy_init()
628 switch (para->type) { in mctl_phy_init()
645 if (para->clk <= 672) in mctl_phy_init()
740 switch (para->type) { in mctl_dfi_init()
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A Ddram_sun4i.c573 if (para->type != DRAM_MEMORY_TYPE_DDR3 || para->rank_num != 1) in dramc_init_helper()
577 mctl_setup_dram_clock(para->clock, para->mbus_clock); in dramc_init_helper()
623 mctl_set_impedance(para->zq, para->odt_en); in dramc_init_helper()
660 if (para->tpr4 & 0x1) in dramc_init_helper()
698 if (!para) in dramc_init()
702 if (para->io_width && para->bus_width && para->density) in dramc_init()
706 para->io_width = 16; in dramc_init()
707 para->bus_width = 32; in dramc_init()
710 para->density = 4096; in dramc_init()
713 para->density = 8192; in dramc_init()
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A Ddram_sun6i.c167 para->rank = 1; in mctl_channel_init()
176 para->chan = 1; in mctl_channel_init()
183 para->bus_width = 16; in mctl_channel_init()
274 MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_ROW(para->rows) | in mctl_com_init()
280 if (para->chan == 1) { in mctl_com_init()
347 para.chan = 1; in sunxi_dram_init()
354 if (para.chan == 2) { in sunxi_dram_init()
362 if (para.chan == 2) in sunxi_dram_init()
365 mctl_com_init(&para); in sunxi_dram_init()
391 for (para.rows = 11; para.rows < 16; para.rows++) { in sunxi_dram_init()
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A Ddram_sunxi_dw.c416 if (!para->dual_rank) in mctl_set_cr()
485 mctl_set_cr(socid, para); in mctl_channel_init()
602 para->dual_rank = 0; in mctl_channel_init()
659 mctl_set_cr(socid, para); in mctl_auto_detect_dram_size_rank()
667 mctl_set_cr(socid, para); in mctl_auto_detect_dram_size_rank()
675 mctl_set_cr(socid, para); in mctl_auto_detect_dram_size_rank()
711 para->dual_rank = 0; in mctl_r40_detect_rank_count()
734 …ctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(&para-… in mctl_auto_detect_dram_size()
834 struct dram_para para = { in sunxi_dram_init() local
893 if (para.dual_rank) in sunxi_dram_init()
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A Ddram_sun50i_h6.c47 mctl_sys_init(para->clk); in mctl_core_init()
48 mctl_com_init(para, config); in mctl_core_init()
49 switch (para->type) { in mctl_core_init()
310 if (para->clk > 408) in mctl_com_init()
312 else if (para->clk > 246) in mctl_com_init()
343 tmp = para->clk * 7 / 2000; in mctl_com_init()
475 if (para->clk <= 792) { in mctl_channel_init()
476 if (para->clk <= 672) { in mctl_channel_init()
477 if (para->clk <= 600) in mctl_channel_init()
528 mctl_bit_delay_set(para); in mctl_channel_init()
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A Ddram_dw_helpers.c12 void mctl_auto_detect_rank_width(const struct dram_para *para, in mctl_auto_detect_rank_width() argument
30 if (mctl_core_init(para, config)) in mctl_auto_detect_rank_width()
36 if (mctl_core_init(para, config)) in mctl_auto_detect_rank_width()
42 if (mctl_core_init(para, config)) in mctl_auto_detect_rank_width()
48 if (mctl_core_init(para, config)) in mctl_auto_detect_rank_width()
87 void mctl_auto_detect_dram_size(const struct dram_para *para, in mctl_auto_detect_dram_size() argument
96 mctl_core_init(para, config); in mctl_auto_detect_dram_size()
122 mctl_core_init(para, config); in mctl_auto_detect_dram_size()
A Ddram_sun55i_a523.c156 val_hi = para->dx_dri; in mctl_phy_configure_odt()
157 val_lo = (para->type != SUNXI_DRAM_TYPE_LPDDR4) ? para->dx_dri : in mctl_phy_configure_odt()
158 (para->tpr1 & 0x1f1f1f1f) ? para->tpr1 : 0x04040404; in mctl_phy_configure_odt()
172 val_lo = para->ca_dri; in mctl_phy_configure_odt()
173 val_hi = para->ca_dri; in mctl_phy_configure_odt()
180 val_hi = para->dx_odt; in mctl_phy_configure_odt()
181 val_lo = (para->type == SUNXI_DRAM_TYPE_LPDDR4) ? 0 : para->dx_odt; in mctl_phy_configure_odt()
861 val = para->tpr0; in mctl_phy_ca_bit_delay_compensation()
863 val = ((para->tpr10 & 0xf0) << 5) | ((para->tpr10 & 0xf) << 1); in mctl_phy_ca_bit_delay_compensation()
872 switch (para->type) { in mctl_phy_ca_bit_delay_compensation()
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/arch/arm/mach-sunxi/dram_timings/
A Da133_lpddr4.c4 void mctl_set_timing_params(const struct dram_para *para) in mctl_set_timing_params() argument
9 bool tpr13_flag1 = para->tpr13 & BIT(28); in mctl_set_timing_params()
10 bool tpr13_flag2 = para->tpr13 & BIT(3); in mctl_set_timing_params()
11 bool tpr13_flag3 = para->tpr13 & BIT(5); in mctl_set_timing_params()
88 writel(para->mr11 << 16 | para->mr12, &mctl_ctl->init[6]); in mctl_set_timing_params()
89 writel(para->tpr1 << 16 | para->mr14, &mctl_ctl->init[7]); in mctl_set_timing_params()
A Dh616_ddr3_1333.c17 void mctl_set_timing_params(const struct dram_para *para) in mctl_set_timing_params() argument
42 u8 trasmax = (para->clk / 2) / 15; /* JEDEC: tREFI * 9 */ in mctl_set_timing_params()
56 if (para->tpr2 & 0x100) { in mctl_set_timing_params()
A Dh616_lpddr3.c17 void mctl_set_timing_params(const struct dram_para *para) in mctl_set_timing_params() argument
42 u8 trasmax = (para->clk / 2) / 16; in mctl_set_timing_params()
A Da133_ddr4.c4 void mctl_set_timing_params(const struct dram_para *para) in mctl_set_timing_params() argument
A Dddr2_v3s.c4 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
A Dddr3_1333.c4 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
A Dlpddr3_stock.c4 void mctl_set_timing_params(uint16_t socid, struct dram_para *para) in mctl_set_timing_params() argument
A Dh616_lpddr4_2133.c15 void mctl_set_timing_params(const struct dram_para *para) in mctl_set_timing_params() argument
/arch/arm/include/asm/arch-sunxi/
A Ddram_dw_helpers.h14 bool mctl_core_init(const struct dram_para *para,
16 void mctl_auto_detect_rank_width(const struct dram_para *para,
18 void mctl_auto_detect_dram_size(const struct dram_para *para,
A Ddram_sun50i_h616.h178 void mctl_set_timing_params(const struct dram_para *para);
A Ddram_sun4i.h178 unsigned long dramc_init(struct dram_para *para);
A Ddram_sunxi_dw.h241 void mctl_set_timing_params(uint16_t socid, struct dram_para *para);
A Ddram_sun50i_a133.h219 void mctl_set_timing_params(const struct dram_para *para);

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