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Searched refs:phy0_ctrl (Results 1 – 1 of 1) sorted by relevance

/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c54 writel(val, &phy0_ctrl->phy_con39); in ddr3_mem_ctrl_init()
60 writel(val, &phy0_ctrl->phy_con42); in ddr3_mem_ctrl_init()
92 writel(val, &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
97 &phy0_ctrl->phy_con12); in ddr3_mem_ctrl_init()
140 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
145 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
151 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
166 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
173 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
178 writel(val, &phy0_ctrl->phy_con1); in ddr3_mem_ctrl_init()
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