Home
last modified time | relevance | path

Searched refs:phy0_dqs (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h89 unsigned phy0_dqs; member
A Dclock_init_exynos5.c191 .phy0_dqs = 0x08080808,
294 .phy0_dqs = 0x08080808,
397 .phy0_dqs = 0x08080808,
A Ddmc_init_ddr3.c79 writel(mem->phy0_dqs, &phy0_ctrl->phy_con4); in ddr3_mem_ctrl_init()

Completed in 708 milliseconds