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Searched refs:phy1_ctrl (Results 1 – 1 of 1) sorted by relevance

/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c55 writel(val, &phy1_ctrl->phy_con39); in ddr3_mem_ctrl_init()
61 writel(val, &phy1_ctrl->phy_con42); in ddr3_mem_ctrl_init()
93 writel(val, &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
99 &phy1_ctrl->phy_con12); in ddr3_mem_ctrl_init()
141 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
146 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
152 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
167 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
174 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
179 writel(val, &phy1_ctrl->phy_con1); in ddr3_mem_ctrl_init()
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