Searched refs:phy1_dq (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A D	clock_init.h	92 unsigned phy1_dq; member
A D	clock_init_exynos5.c	194 .phy1_dq = 0x08080808, 297 .phy1_dq = 0x08080808, 400 .phy1_dq = 0x08080808,
A D	dmc_init_ddr3.c	83 writel(mem->phy1_dq, &phy1_ctrl->phy_con6); in ddr3_mem_ctrl_init()

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