| /arch/arm/mach-uniphier/dram/ |
| A D | ddrphy-ld4.c | 48 writel(0x0300c473, phy_base + PHY_PGCR1); in uniphier_ld4_ddrphy_init()
49 writel(ddrphy_ptr0[freq_e], phy_base + PHY_PTR0); in uniphier_ld4_ddrphy_init()
51 writel(0x00083DEF, phy_base + PHY_PTR2); in uniphier_ld4_ddrphy_init()
54 writel(0xF004001A, phy_base + PHY_DSGCR); in uniphier_ld4_ddrphy_init()
57 tmp = readl(phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
60 writel(tmp, phy_base + PHY_DXCCR); in uniphier_ld4_ddrphy_init()
62 writel(0x0000040B, phy_base + PHY_DCR); in uniphier_ld4_ddrphy_init()
66 writel(ddrphy_mr0[freq_e], phy_base + PHY_MR0); in uniphier_ld4_ddrphy_init()
67 writel(0x00000006, phy_base + PHY_MR1); in uniphier_ld4_ddrphy_init()
68 writel(ddrphy_mr2[freq_e], phy_base + PHY_MR2); in uniphier_ld4_ddrphy_init()
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| A D | umc-pxs2.c | 64 tmp = readl(phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
66 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
71 writel(tmp, phy_base + MPHY_PGCR0); in ddrphy_fifo_reset()
80 tmp = readl(phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
87 writel(tmp, phy_base + MPHY_PGCR1); in ddrphy_vt_ctrl()
101 ddrphy_vt_ctrl(phy_base, 0); in ddrphy_dqs_delay_fixup()
113 ddrphy_vt_ctrl(phy_base, 1); in ddrphy_dqs_delay_fixup()
208 zq_base = phy_base + MPHY_ZQ_BASE; in ddrphy_init()
565 ddrphy_dram_init(phy_base); in umc_ch_init()
575 ret = ddrphy_training(phy_base); in umc_ch_init()
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| A D | ddrphy-training.c | 21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
23 void __iomem *dx_base = phy_base + PHY_DX_BASE; in ddrphy_prepare_training()
37 tmp = readl(phy_base + PHY_DTCR); in ddrphy_prepare_training()
46 writel(tmp, phy_base + PHY_DTCR); in ddrphy_prepare_training()
107 int ddrphy_training(void __iomem *phy_base) in ddrphy_training() argument
123 writel(init_flag, phy_base + PHY_PIR); in ddrphy_training()
131 pgsr0 = readl(phy_base + PHY_PGSR0); in ddrphy_training()
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| A D | ddrphy-init.h | 12 int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
14 int ddrphy_training(void __iomem *phy_base);
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| A D | cmd_ddrmphy.c | 74 void __iomem *phy_base, *dx_base; in dump_loop() local
78 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
79 dx_base = phy_base + MPHY_DX_BASE; in dump_loop()
88 iounmap(phy_base); in dump_loop()
94 void __iomem *phy_base, *zq_base; in zq_dump() local
103 zq_base = phy_base + MPHY_ZQ_BASE; in zq_dump()
124 iounmap(phy_base); in zq_dump()
237 void __iomem *reg = phy_base + ofst; \
243 void __iomem *phy_base; in reg_dump() local
252 ptr_to_uint(phy_base)); in reg_dump()
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| A D | cmd_ddrphy.c | 89 void __iomem *phy_base, *dx_base; in dump_loop() local
93 phy_base = ioremap(param->phy[phy].base, SZ_4K); in dump_loop()
94 dx_base = phy_base + PHY_DX_BASE; in dump_loop()
103 iounmap(phy_base); in dump_loop()
204 { int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
212 void __iomem *reg = phy_base + ofst; \
219 void __iomem *phy_base; in reg_dump() local
225 phy_base = ioremap(param->phy[phy].base, SZ_4K); in reg_dump()
228 phy, ptr_to_uint(phy_base)); in reg_dump()
261 iounmap(phy_base); in reg_dump()
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| A D | umc-pro4.c | 134 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
146 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
150 ddrphy_prepare_training(phy_base, phy); in umc_ch_init()
151 ret = ddrphy_training(phy_base); in umc_ch_init()
155 phy_base += 0x00001000; in umc_ch_init()
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| A D | umc-ld4.c | 147 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
156 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
160 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
161 ret = ddrphy_training(phy_base); in umc_ch_init()
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| A D | umc-sld8.c | 150 void __iomem *phy_base = dc_base + 0x00001000; in umc_ch_init() local
159 ret = uniphier_ld4_ddrphy_init(phy_base, freq, ddr3plus); in umc_ch_init()
163 ddrphy_prepare_training(phy_base, umc_get_rank(ch)); in umc_ch_init()
164 ret = ddrphy_training(phy_base); in umc_ch_init()
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| /arch/arm/mach-mvebu/alleycat5/ |
| A D | soc.c | 270 u64 new_val, phy_base = 0x7F080800; in mach_cpu_init() local
278 for (phy_i = 0; phy_i < 2; phy_i++, phy_base += USB_STEPPING) { in mach_cpu_init()
279 WRITE_MASK(phy_base + 0x4, 0x3, 0x2); in mach_cpu_init()
280 WRITE_MASK(phy_base + 0xC, 0x3000000, 0x2000000); in mach_cpu_init()
281 WRITE_MASK(phy_base + 0x1C, 0x3, 0x2); in mach_cpu_init()
282 WRITE_MASK(phy_base + 0x0, 0x1FF007F, 0x600005); in mach_cpu_init()
283 WRITE_MASK(phy_base + 0xC, 0x000F000, 0x0002000); in mach_cpu_init()
285 WRITE_MASK(phy_base + 0x8, 0x700, 0x400) in mach_cpu_init()
286 WRITE_MASK(phy_base + 0x14, 0x000000F, 0x000000a); in mach_cpu_init()
288 WRITE_MASK(phy_base + 0xC, 0x3700000, 0x3400000); in mach_cpu_init()
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| /arch/arm/include/asm/arch-rockchip/ |
| A D | sdram_phy_px30.h | 59 void phy_soft_reset(void __iomem *phy_base);
60 void phy_dram_set_bw(void __iomem *phy_base, u32 bw);
61 void phy_cfg(void __iomem *phy_base,
64 int phy_data_training(void __iomem *phy_base, u32 cs, u32 dramtype);
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