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Searched refs:phy_con0 (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c140 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
141 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
151 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
152 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
173 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
174 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
490 val = readl(&phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
493 writel(val, &phy0_ctrl->phy_con0); in ddr3_mem_ctrl_init()
495 val = readl(&phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
498 writel(val, &phy1_ctrl->phy_con0); in ddr3_mem_ctrl_init()
[all …]
/arch/arm/mach-exynos/include/mach/
A Ddmc.h330 unsigned int phy_con0; member
377 unsigned int phy_con0; member
/arch/arm/mach-imx/mx7/
A Dddr.c94 writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0); in mx7_dram_cfg()
/arch/arm/include/asm/arch-mx7/
A Dmx7-ddr.h127 u32 phy_con0; /* 0x0000 */ member

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