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Searched refs:phy_con10 (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/include/mach/
A Ddmc.h340 unsigned int phy_con10; member
387 unsigned int phy_con10; member
/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c85 writel(mem->phy0_tFS, &phy0_ctrl->phy_con10); in ddr3_mem_ctrl_init()
86 writel(mem->phy1_tFS, &phy1_ctrl->phy_con10); in ddr3_mem_ctrl_init()
292 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
293 clrbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()

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