Searched refs:phy_con2 (Results 1 – 2 of 2) sorted by relevance
| /arch/arm/mach-exynos/ |
| A D | dmc_init_ddr3.c | 145 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
146 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
166 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
167 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
698 writel(val, &phy0_ctrl->phy_con2); in ddr3_mem_ctrl_init()
699 writel(val, &phy1_ctrl->phy_con2); in ddr3_mem_ctrl_init()
729 setbits_le32(&phy0_ctrl->phy_con2, RDLVL_GATE_EN); in ddr3_mem_ctrl_init()
730 setbits_le32(&phy1_ctrl->phy_con2, RDLVL_GATE_EN); in ddr3_mem_ctrl_init()
789 setbits_le32(&phy0_ctrl->phy_con2, DLL_DESKEW_EN); in ddr3_mem_ctrl_init()
790 setbits_le32(&phy1_ctrl->phy_con2, DLL_DESKEW_EN); in ddr3_mem_ctrl_init()
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| /arch/arm/mach-exynos/include/mach/ |
| A D | dmc.h | 332 unsigned int phy_con2; member
379 unsigned int phy_con2; member
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