Searched refs:phy_ctrl (Results 1 – 17 of 17) sorted by relevance
| /arch/arm/mach-exynos/ |
| A D | dmc_init_ddr3.c | 280 *phy_ctrl) in dmc_get_read_offset_value()
282 return readl(&phy_ctrl->phy_con4); in dmc_get_read_offset_value()
292 setbits_le32(&phy_ctrl->phy_con10, PHY_CON10_CTRL_OFFSETR3); in ddr_phy_set_do_resync()
307 writel(offset, &phy_ctrl->phy_con4); in dmc_set_read_offset_value()
308 ddr_phy_set_do_resync(phy_ctrl); in dmc_set_read_offset_value()
359 dmc_set_read_offset_value(phy_ctrl, DEFAULT_DQS_X4); in test_shifts()
368 offsetr = dmc_get_read_offset_value(phy_ctrl); in test_shifts()
371 dmc_set_read_offset_value(phy_ctrl, offsetr); in test_shifts()
423 test_shifts(phy_ctrl, ch, left_limit, right_limit, left); in software_find_read_offset()
424 test_shifts(phy_ctrl, ch, right_limit, left_limit, right); in software_find_read_offset()
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| /arch/arm/include/asm/arch-aspeed/ |
| A D | sdram_ast2500.h | 120 u32 phy_ctrl[4]; member
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| A D | sdram_ast2600.h | 156 u32 phy_ctrl[4]; /* offset 0x60 ~ 0x6C */ member
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| /arch/arm/dts/ |
| A D | sun8i-a23.dtsi | 103 reg-names = "phy_ctrl", "pmu1";
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| A D | sun8i-a33.dtsi | 431 reg-names = "phy_ctrl", "pmu1";
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| A D | am33xx.dtsi | 408 reg-names = "phy_ctrl", "wakeup";
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| A D | sunxi-h3-h5.dtsi | 274 reg-names = "phy_ctrl",
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| A D | sun50i-h6.dtsi | 682 reg-names = "phy_ctrl",
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| A D | sun8i-a83t.dtsi | 643 reg-names = "phy_ctrl",
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| A D | sun8i-r40.dtsi | 413 reg-names = "phy_ctrl",
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| A D | sun50i-a64.dtsi | 587 reg-names = "phy_ctrl",
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| A D | sun6i-a31.dtsi | 527 reg-names = "phy_ctrl",
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| A D | sun7i-a20.dtsi | 610 reg-names = "phy_ctrl", "pmu1", "pmu2";
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| /arch/arm/mach-exynos/include/mach/ |
| A D | dp.h | 192 unsigned int phy_ctrl; member
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| /arch/riscv/dts/ |
| A D | sunxi-d1s-t113.dtsi | 550 reg-names = "phy_ctrl",
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| /arch/mips/mach-octeon/include/mach/ |
| A D | cvmx-pciercx-defs.h | 5455 u32 phy_ctrl : 32; member
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| A D | cvmx-pcieepx-defs.h | 6717 u32 phy_ctrl : 32; member
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