Searched refs:phycontrol0 (Results 1 – 5 of 5) sorted by relevance
| /arch/arm/mach-exynos/ |
| A D | dmc_common.c | 75 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll() argument
81 writel(val, phycontrol0); in update_reset_dll()
85 val = readl(phycontrol0); in update_reset_dll()
87 writel(val, phycontrol0); in update_reset_dll()
90 val = readl(phycontrol0); in update_reset_dll()
92 writel(val, phycontrol0); in update_reset_dll()
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| A D | dmc_init_exynos4.c | 60 &dmc->phycontrol0); in phy_control_reset()
62 &dmc->phycontrol0); in phy_control_reset()
108 writel((mem.control0 | CTRL_START | CTRL_DLL_ON), &dmc->phycontrol0); in dmc_init()
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| A D | dmc_init_ddr3.c | 76 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
101 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
210 update_reset_dll(&dmc->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
544 writel(val, &drex0->phycontrol0); in ddr3_mem_ctrl_init()
545 writel(val, &drex1->phycontrol0); in ddr3_mem_ctrl_init()
566 update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
567 update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3); in ddr3_mem_ctrl_init()
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| A D | exynos5_setup.h | 941 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
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| /arch/arm/mach-exynos/include/mach/ |
| A D | dmc.h | 12 unsigned int phycontrol0; member
121 unsigned int phycontrol0; member
215 unsigned int phycontrol0; member
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