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Searched refs:pll0div_read (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-keystone/
A Dclock.c371 freq = pll_freq_get(CORE_PLL) / pll0div_read(1); in ks_clk_get_rate()
374 return pll_freq_get(CORE_PLL) / pll0div_read(2); in ks_clk_get_rate()
377 freq = pll_freq_get(CORE_PLL) / pll0div_read(3); in ks_clk_get_rate()
380 freq = pll_freq_get(CORE_PLL) / pll0div_read(4); in ks_clk_get_rate()
/arch/arm/mach-keystone/include/mach/
A Dclock_defs.h70 #define pll0div_read(N) ((pllctl_reg_read(CORE_PLL, div##N) & 0xff) + 1) macro

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