Searched refs:pll_base (Results 1 – 8 of 8) sorted by relevance
| /arch/arm/mach-davinci/ |
| A D | cpu.c | 43 unsigned int pll_base; in clk_get() local
51 pll_base = (unsigned int)davinci_pllc1_regs; in clk_get()
53 pll_base = (unsigned int)davinci_pllc0_regs; in clk_get()
61 pre_div = (readl(pll_base + PLLC_PREDIV) & in clk_get()
63 pllm = readl(pll_base + PLLC_PLLM) + 1; in clk_get()
71 post_div = (readl(pll_base + PLLC_POSTDIV) & in clk_get()
79 pll_out /= (readl(pll_base + sysdiv[id - 1]) & in clk_get()
|
| /arch/arm/mach-tegra/ |
| A D | clock.c | 110 data = readl(&pll->pll_base); in clock_ll_read_pll()
162 writel(data, &pll->pll_base); in clock_start_pll()
165 writel(data, &simple_pll->pll_base); in clock_start_pll()
586 base = readl(&pll->pll_base); in clock_get_rate()
588 base = readl(&simple_pll->pll_base); in clock_get_rate()
645 base_reg = readl(&pll->pll_base); in clock_set_rate()
666 if (base_reg != readl(&pll->pll_base)) in clock_set_rate()
675 writel(base_reg, &pll->pll_base); in clock_set_rate()
695 writel(base_reg, &pll->pll_base); in clock_set_rate()
702 writel(base_reg, &pll->pll_base); in clock_set_rate()
[all …]
|
| A D | cpu.c | 222 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { in pllx_set_rate()
232 writel(reg, &pll->pll_base); in pllx_set_rate()
250 reg = readl(&pll->pll_base); in pllx_set_rate()
252 writel(reg, &pll->pll_base); in pllx_set_rate()
263 reg = readl(&pll->pll_base); in pllx_set_rate()
265 writel(reg, &pll->pll_base); in pllx_set_rate()
|
| /arch/arm/mach-imx/imx8m/ |
| A D | clock_imx8mm.c | 74 void *pll_base; in fracpll_configure() local
94 pll_base = &ana_pll->dram_pll_gnrl_ctl; in fracpll_configure()
97 pll_base = &ana_pll->video_pll1_gnrl_ctl; in fracpll_configure()
103 tmp = readl(pll_base); in fracpll_configure()
105 writel(tmp, pll_base); in fracpll_configure()
109 writel(tmp, pll_base); in fracpll_configure()
113 writel(div_val, pll_base + 4); in fracpll_configure()
114 writel(rate->kdiv << KDIV_SHIFT, pll_base + 8); in fracpll_configure()
120 writel(tmp, pll_base); in fracpll_configure()
123 while (!(readl(pll_base) & LOCK_STATUS)) in fracpll_configure()
[all …]
|
| /arch/arm/mach-tegra/tegra20/ |
| A D | warmboot_avp.c | 188 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
191 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
193 writel(pllx_base.word, &clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in wb_start()
|
| /arch/arm/include/asm/arch-tegra/ |
| A D | clk_rst.h | 12 uint pll_base; /* the control register */ member
20 uint pll_base; /* the control register */ member
|
| /arch/arm/mach-tegra/tegra114/ |
| A D | cpu.c | 66 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
|
| /arch/arm/mach-tegra/tegra124/ |
| A D | cpu.c | 59 reg = readl(&clkrst->crc_pll_simple[SIMPLE_PLLX].pll_base); in enable_cpu_clocks()
|
Completed in 21 milliseconds