Searched refs:pll_rate (Results 1 – 3 of 3) sorted by relevance
| /arch/arm/mach-tegra/ |
| A D | clock.c | 27 static unsigned pll_rate[CLOCK_ID_COUNT]; variable
283 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
322 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate()
474 parent_rate = pll_rate[parent]; in clock_adjust_periph_pll_div()
720 pll_rate[clkid] = clock_get_rate(clkid); in clock_set_rate()
801 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768; in clock_init()
808 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]); in clock_init()
809 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]); in clock_init()
811 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]); in clock_init()
813 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]); in clock_init()
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| /arch/arm/mach-nexell/ |
| A D | clock.c | 330 static unsigned int pll_rate(unsigned int plln, unsigned int xtal) in pll_rate() function
372 #define PLLN_RATE(n) (pll_rate(n, CONFIG_SYS_PLLFIN)) /* 0~ 3 */
373 #define CPU_FCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
375 #define CPU_BCLK_RATE(n) (pll_rate(pll_dvo(n), CONFIG_SYS_PLLFIN) / \
379 #define MEM_FCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
383 #define MEM_DCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
386 #define MEM_BCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
390 #define MEM_PCLK_RATE() (pll_rate(pll_dvo(DIV_MEM), CONFIG_SYS_PLLFIN) / \
396 #define BUS_BCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
398 #define BUS_PCLK_RATE() (pll_rate(pll_dvo(DIV_BUS), CONFIG_SYS_PLLFIN) / \
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| /arch/arm/mach-imx/mx6/ |
| A D | clock.c | 423 u32 pll_rate; in get_lcd_clk() local
432 pll_rate = decode_pll(PLL_VIDEO, MXC_HCLK); in get_lcd_clk()
468 return DIV_ROUND_UP_ULL((u64)pll_rate, (postd + 1) * (pred + 1)); in get_lcd_clk()
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