Searched refs:pll_regs (Results 1 – 3 of 3) sorted by relevance
| /arch/mips/mach-ath79/ar934x/ |
| A D | clk.c | 112 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in ar934x_pll_init() local
172 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
174 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
176 setbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
181 pll_regs + AR934X_PLL_CPU_CONFIG_REG); in ar934x_pll_init()
184 pll_regs + AR934X_PLL_DDR_CONFIG_REG); in ar934x_pll_init()
195 pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG); in ar934x_pll_init()
202 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
204 clrbits_be32(pll_regs + AR934X_PLL_CPU_DDR_CLK_CTRL_REG, in ar934x_pll_init()
212 pll_regs + AR934X_PLL_DDR_DIT_FRAC_REG); in ar934x_pll_init()
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| /arch/mips/mach-ath79/qca956x/ |
| A D | clk.c | 187 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in set_val() local
189 writel((readl(pll_regs + _reg) & (~(_mask))) | _val, pll_regs + _reg); in set_val()
223 void __iomem *pll_regs = map_physmem(AR71XX_PLL_BASE, in qca956x_pll_init() local
276 CPU_DDR_CLOCK_CONTROL_AHB_PLL_BYPASS_SET(1), pll_regs + QCA956X_PLL_CLK_CTRL_REG); in qca956x_pll_init()
279 writel(DDR_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_DDR_DIT_FRAC_REG); in qca956x_pll_init()
280 writel(DDR_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_DDR_DIT2_FRAC_REG); in qca956x_pll_init()
283 writel(CPU_PLL_DITHER1_VAL, pll_regs + QCA956X_PLL_CPU_DIT_FRAC_REG); in qca956x_pll_init()
284 writel(CPU_PLL_DITHER2_VAL, pll_regs + QCA956X_PLL_CPU_DIT2_FRAC_REG); in qca956x_pll_init()
302 while (readl(pll_regs + QCA956X_PLL_CPU_CONFIG_REG) & 0x8000000) in qca956x_pll_init()
305 while (readl(pll_regs + QCA956X_PLL_DDR_CONFIG_REG) & 0x8000000) in qca956x_pll_init()
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| /arch/arm/include/asm/arch-mx27/ |
| A D | imx-regs.h | 109 struct pll_regs { struct
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