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Searched refs:pll_status (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-imx/imx9/
A Dclock.c55 u32 pll_status; in decode_pll_vco() local
61 pll_status = readl(&reg->pll_status); in decode_pll_vco()
67 if (!(pll_status & PLL_STATUS_PLL_LOCK)) in decode_pll_vco()
191 u32 pll_status; in configure_intpll() local
235 pll_status = readl(&reg->pll_status); in configure_intpll()
254 u32 pll_status; in configure_fracpll() local
308 pll_status = readl(&reg->pll_status); in configure_fracpll()
313 pll_status = readl(&reg->pll_status); in configure_fracpll()
316 pll_status, rate->mfn); in configure_fracpll()
401 u32 pll_status; in update_fracpll_mfn() local
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/arch/powerpc/cpu/mpc85xx/
A Dfsl_corenet2_serdes.c206 u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1; in serdes_init() local
232 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
234 pll_num, pll_status); in serdes_init()
239 switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) { in serdes_init()
319 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
321 pll_num, pll_status); in serdes_init()
323 if ((pll_status & SRDS_PLLCR0_PLL_LCK) == 0) in serdes_init()
/arch/arm/mach-exynos/include/mach/
A Ddp_info.h87 enum pll_status { enum
/arch/arm/include/asm/arch-imx9/
A Dclock.h138 u32 pll_status; member

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