| /arch/microblaze/cpu/ |
| A D | irq.S | 13 addik r1, r1, -124
14 swi r2, r1, 4
15 swi r3, r1, 8
16 swi r4, r1, 12
17 swi r5, r1, 16
18 swi r6, r1, 20
19 swi r7, r1, 24
20 swi r8, r1, 28
21 swi r9, r1, 32
22 swi r10, r1, 36
[all …]
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| A D | start.S | 32 add r1, r0, r20
66 addi r1, r1, -4 /* Decrement SP to top of memory */
70 add r5, r0, r1
76 add r1, r0, r3
77 mts rshr, r1
78 addi r1, r1, -4
155 addik r1, r1, -32
156 swi r2, r1, 4
157 swi r3, r1, 8
262 addik r1, r1, 32
[all …]
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| /arch/arm/mach-imx/mx5/ |
| A D | lowlevel_init.S | 129 ands r1, r1, #0x1
141 ands r1, r1, #0x1
156 3: subs r1, r1, #1
273 add r1, r1, #0x00000F0
323 and r1, r1, #0xfcffffff
324 orr r1, r1, #0x01000000
351 and r1, r1, #0xffffffc0
352 orr r1, r1, #0x0a
371 add r1, r1, #0x00000F0
384 orr r1, r1, #1 << 23
[all …]
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| /arch/arm/mach-uniphier/arm32/ |
| A D | debug_ll.S | 35 and r1, r1, #SG_REVISION_TYPE_MASK
36 mov r1, r1, lsr #SG_REVISION_TYPE_SHIFT
45 orr r1, r1, #1
63 mov r1, #1
68 orr r1, r1, #SC_CLKCTRL_CEN_PERI
83 orr r1, r1, #1
109 orr r1, r1, #SC_CLKCTRL_CEN_PERI
124 orr r1, r1, #1
134 orr r1, r1, #SC_CLKCTRL_CEN_PERI
149 orr r1, r1, #1
[all …]
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| A D | psci_smp.S | 14 mrc p15, 0, r1, c1, c0, 0 @ SCTLR (System Control Register)
15 orr r1, r1, #CR_I @ Enable ICache
16 bic r1, r1, #(CR_C | CR_M) @ Disable MMU and Dcache
17 mcr p15, 0, r1, c1, c0, 0
26 mrc p15, 0, r1, c0, c0, 5 @ MPIDR (Multiprocessor Affinity Reg)
27 and r1, r1, #0xff
31 str r0, [r2, r1, lsl #2]
35 cmp r0, r1
|
| /arch/arm/mach-aspeed/ast2600/ |
| A D | lowlevel_init.S | 57 str r0, [r1]
59 str r0, [r1]
64 ldr r1, [r1]
66 lsr r1, #0x8
69 cmp r1, #0x0
74 cmp r1, #0x1
79 cmp r1, #0x2
84 cmp r1, #0x3
89 cmp r1, #0x4
135 cmp r1, r0
[all …]
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| /arch/arm/lib/ |
| A D | memset.S | 27 1: orr r1, r1, r1, lsl #8
28 orr r1, r1, r1, lsl #16
29 mov r3, r1
39 mov r8, r1
40 mov lr, r1
67 mov r4, r1
68 mov r5, r1
69 mov r6, r1
70 mov r7, r1
71 mov r8, r1
[all …]
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| A D | debug.S | 32 mov r1, #8
37 mov r1, #4
42 mov r1, #2
45 mov r1, #0
46 strb r1, [r3]
49 cmp r1, #10
50 addlt r1, r1, #'0'
51 addge r1, r1, #'a' - 10
76 teqne r1, #0
83 mov r1, r0
[all …]
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| A D | lib1funcs.S | 325 sub r1, r1, r3
341 sub r1, r1, r3
369 lsrs r1, r1, #1
370 lsls r1, r1, #1
372 lsls r1, r1, #1
383 lsrs r1, r1, #1
384 lsls r1, r1, #1
386 lsls r1, r1, #1
397 lsrs r1, r1, #1
399 lsls r1, r1, #1
[all …]
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| A D | relocate.S | 35 ldr r1, =V7M_SCB_BASE
36 str r0, [r1, V7M_SCB_VTOR]
58 stmia r1!, {r2-r8,r10}
60 stmia r1!, {r2-r8,r10}
97 ldr r1, _rel_dyn_start_ofs
99 ldr r1, _rel_dyn_end_ofs
103 and r1, r1, #0xff
104 cmp r1, #R_ARM_RELATIVE
109 ldr r1, [r0]
110 add r1, r1, r4
[all …]
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| A D | memcpy.S | 61 cmp r0, r1
69 PLD( pld [r1, #0] )
71 ands ip, r1, #3
86 PLD( pld [r1, #0] )
88 PLD( pld [r1, #28] )
90 PLD( pld [r1, #60] )
91 PLD( pld [r1, #92] )
163 ands ip, r1, #3
166 10: bic r1, r1, #3
186 PLD( pld [r1, #0] )
[all …]
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| /arch/arm/mach-npcm/npcm7xx/ |
| A D | l2_cache_pl310_init.S | 22 LDR r1, =0x0
23 STR r1, [r0,#0x100]
28 LDR r1, =0x02050000
29 ORR r1, r1, #(1 << 29) @ Instruction prefetch enable
30 ORR r1, r1, #(1 << 28) @ Data prefetch enable
31 ORR r1, r1, #(1 << 22) @ cache replacement policy
38 LDR r1, =0x00000000
49 LDR r1, =0xFFFF
53 TST r1, #1
57 LDR r1, =0x0
[all …]
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| /arch/arm/mach-zynq/ |
| A D | lowlevel_init.S | 13 mrc p15, 0, r1, c1, c0, 2
14 orr r1, r1, #(0x3 << 20)
15 orr r1, r1, #(0x3 << 20)
16 mcr p15, 0, r1, c1, c0, 2
18 fmrx r1, FPEXC
19 orr r1,r1, #(1<<30)
20 fmxr FPEXC, r1
|
| /arch/arm/mach-aspeed/ast2500/ |
| A D | lowlevel_init.S | 19 ldr r1, =SCU_UNLOCK_VALUE
20 str r1, [r0]
24 ldr r1, [r0]
25 orr r1, #0x80
26 str r1, [r0]
30 ldr r1, [r0]
31 tst r1, #(0x1 << 25)
33 movne r1, #(0x1 << 14)
34 strne r1, [r0]
38 mov r1, #0x0
[all …]
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| /arch/arm/mach-orion5x/ |
| A D | lowlevel_init.S | 181 mov r1, r0
182 mov r1, r1, LSL #9
184 orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
187 orr r0, r0, r1
203 mov r1, r0
204 mov r1, r1, LSL #9
205 mov r1, r1, LSR #26
206 orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
209 orr r0, r0, r1
226 orr r0, r0, r1
[all …]
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| /arch/arm/mach-mediatek/mt7629/ |
| A D | lowlevel_init.S | 33 orr r0, r1, #1
64 mov r1, #0xf0
65 str r1, [r2, #4]
66 mov r1, #1
67 str r1, [r2, #0]
69 ldr r1, [r2]
70 orr r1, #1
71 str r1, [r2]
93 cmp r2, r1
97 ldr r1, [r0]
[all …]
|
| /arch/powerpc/lib/ |
| A D | ticks.S | 32 stwu r1, -16(r1)
34 stw r0, 20(r1) /* Use r0 or GDB will be unhappy */
35 stw r14, 12(r1) /* save used registers */
36 stw r15, 8(r1)
52 lwz r15, 8(r1) /* restore saved registers */
53 lwz r14, 12(r1)
54 lwz r0, 20(r1)
55 addi r1,r1,16
|
| /arch/arm/mach-lpc32xx/ |
| A D | lowlevel_init.S | 23 ldr r1, =0x40004040
24 str r0, [r1]
28 ldr r1, =0x40004058
29 str r0, [r1]
33 ldr r0, [r1]
38 ldr r1, =0x40004044
39 ldr r0, [r1]
41 str r0, [r1]
|
| /arch/arm/mach-exynos/ |
| A D | sec_boot.S | 13 adr r1, code_end @ r1: source address (end)
18 cmp r0, r1
109 ldr r1, [r0]
110 cmp r1, #0x0
111 movne r1, #0x0
112 strne r1, [r0]
114 ldrne r1, =(0x10040000 + 0x800)
115 ldrne pc, [r1]
120 ldr r1, [r0]
121 cmp r1, #0x0
[all …]
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| /arch/sh/lib/ |
| A D | udivsi3_i4i.S | 51 mov r5,r1
72 mov.l @(r0,r1),r1
87 shld r1,r0
104 mov r5,r1
122 and r1,r0
137 mov r0,r1
218 mov.l @(r0,r1),r1
267 or r4,r1
270 rotcl r1
299 shll8 r1
[all …]
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| A D | udiv_qrnnd.S | 30 extu.w r0,r1
33 0: rotcl r1
34 mulu.w r1,r5
42 add #-1,r1
44 1: add #-1,r1
50 swap.w r4,r1
51 xtrct r0,r1
53 mov r1,r0
55 mov #-1,r1
57 shlr16 r1
|
| /arch/arm/cpu/armv7/ |
| A D | nonsec_virt.S | 55 push {r0, r1, r2, ip}
57 pop {r0, r1, r2, ip}
108 mov r0, r1
109 mov r1, r2
177 mov r1, #0xff
181 movw r1, #0x3fff
182 movt r1, #0x0004
183 orr r0, r0, r1
213 ldr r1, [r1]
215 rev r1, r1
[all …]
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| /arch/arm/mach-renesas/ |
| A D | lowlevel_init_ca15.S | 28 ldr r1, =0xe6180000 /* sysc */
29 1: ldr r0, [r1, #0x20] /* sbar */
40 ldr r1, [r2]
41 and r1, r1, #0x7F00
42 lsrs r1, r1, #8
43 cmp r1, #0x4C /* 0x4C is ID of r8a7794 */
60 and r1, r0, #7
61 cmp r1, #3 /* has already been set up */
|
| /arch/arm/mach-at91/arm920t/ |
| A D | lowlevel_init.S | 32 ldr r1, =AT91_ASM_PMC_MOR
49 ldr r1, _MTEXT_BASE
50 sub r0, r0, r1
52 sub r2, r2, r1
55 ldr r1, [r0], #4
58 str r3, [r1]
68 ldr r1, _MTEXT_BASE
69 sub r0, r0, r1
71 sub r2, r2, r1
74 ldr r1, [r0], #4
[all …]
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| /arch/arm/cpu/armv7/sunxi/ |
| A D | fel_utils.S | 28 mov lr, r1
30 ldr r1, [r0, #16]
31 mcr p15, 0, r1, c12, c0, 0 @ Write VBAR
32 ldr r1, [r0, #12]
33 mcr p15, 0, r1, c1, c0, 0 @ Write CP15 SCTLR Register
34 ldr r1, [r0, #8]
35 msr cpsr, r1 @ Write CPSR
|