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Searched refs:r3 (Results 1 – 25 of 65) sorted by relevance

123

/arch/powerpc/cpu/mpc85xx/
A Drelease.S33 oris r3, r3, 0x0080
53 ori r3, r3, HID1_MBDD@l
60 oris r3,r3,0x0100
66 rlwinm r3,r3,0,0xff
93 ori r3,r3,BUCSR_ENABLE@l
142 lwz r3,0(r3)
221 rlwinm r3,r3,0,0xf0
233 oris r3,r3,(L1CSR2_DCWS)@h
245 andis. r3,r3,(L1CSR2_DCWS)@h
248 oris r3, r3, 0x8000
[all …]
A Dstart.S184 rlwinm r3,r3,0,0xff
237 or r3, r2, r3
515 addi r3, r3, 1
1262 subi r3,r3,16
1471 andc r3,r3,r4
1556 lhbrx r3,0,r3
1574 lwbrx r3,0,r3
1676 andc r3,r3,r0
1726 addi r3,r3,-4
1742 addi r3,r3,-4
[all …]
/arch/powerpc/cpu/mpc83xx/
A Dstart.S110 andc r3, r3, r0
728 andc r3, r3, r4
741 andc r3, r3, r4
757 andc r3, r3, r5
769 andc r3, r3, r5
890 andc r3,r3,r0
926 addi r3,r3,-4
943 addi r3,r3,-4
969 addi r3, r3, 4
1061 addi r3, r3, 32
[all …]
/arch/arm/mach-orion5x/
A Dlowlevel_init.S79 ldr r3, =0xD0000000
80 add r3, r3, #0x20000
81 str r2, [r3, #0x80]
84 add r3, r2, #0x01000
88 str r0, [r3, #0x480]
91 add r3, r2, #0x31000
95 str r0, [r3, #0xd00]
98 add r3, r2, #0x01000
102 str r0, [r3, #0x504]
103 str r0, [r3, #0x50C]
[all …]
/arch/powerpc/lib/
A Dppccache.S23 dcbf 0,r3
34 dcbi 0,r3
46 dcbz 0,r3
69 andc r3,r3,r5
70 subf r4,r3,r4
76 1: dcbf 0,r3
77 addi r3,r3,L1_CACHE_BYTES
93 andc r3,r3,r5
94 subf r4,r3,r4
101 1: dcbi 0,r3
[all …]
A Dppcstring.S12 addi r5,r3,-1
25 addi r6,r3,-1
35 addi r5,r3,-1
49 addi r5,r3,-1
52 cmpwi 1,r3,0
54 subf. r3,r0,r3
65 subf r3,r3,r4
188 subf. r3,r0,r3
191 2: li r3,0
199 addi r3,r3,-1
[all …]
A D_ashldi3.S34 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
38 or r3,r3,r6 # MSW |= t1
40 or r3,r3,r7 # MSW |= t2
A Dticks.S20 1: mftbu r3
23 cmp 0,r3,r5
37 mr r14, r3 /* save tick count */
42 addze r15, r3 /* and end time upper */
49 subfe. r3, r3, r15
A D_lshrdi3.S36 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
37 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
39 srw r3,r3,r5 # MSW = MSW >> count
A D_ashrdi3.S36 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
38 sraw r7,r3,r7 # t2 = MSW >> (count-32)
41 sraw r3,r3,r5 # MSW = MSW >> count
/arch/powerpc/cpu/mpc8xx/
A Dstart.S74 mtmsr r3
118 ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
119 addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
120 mtlr r3
145 ori r3, r3, CFG_SYS_INIT_SP@l
396 andc r3,r3,r0
397 mr r4,r3
403 mr r4,r3
433 addi r3,r3,-4
449 addi r3,r3,-4
[all …]
/arch/arm/include/asm/arch-mx6/
A Dmx6_plugin.S46 ldr r3, =ROM_VERSION_OFFSET
47 ldr r4, [r3]
50 ldr r3, =0x00900b00
52 str r4, [r3, #0x5c]
54 ldr r3, =0x00900800
56 str r4, [r3, #0xc0]
65 ldr r4, [r3]
67 ldr r3, =ROM_VERSION_TO12
68 cmp r4, r3
72 ldr r3, =ROM_VERSION_TO15
[all …]
/arch/nios2/cpu/
A Dexceptions.S27 stw r3, 12(sp)
70 ori r3, r3, %lo(external_interrupt)
72 callr r3
79 addi r3, r3, -4
86 ori r3, r3, %lo(OPC_TRAP)
89 bne r1, r3, 1f
91 ori r3, r3, %lo(trap_handler)
93 callr r3
99 ori r3, r3, %lo(soft_emulation)
101 callr r3
[all …]
/arch/arm/mach-at91/arm926ejs/
A Dlowlevel_init.S46 ldr r3, [r0], #4
47 str r3, [r1]
76 ldr r3, [r2]
77 and r3, r6, r3
94 ldr r3, [r2]
95 and r3, r6, r3
114 ldr r3, [r2]
115 and r3, r6, r3
125 ldr r3, [r2]
126 and r3, r6, r3
[all …]
/arch/arm/lib/
A Dmemset.S21 ands r3, r0, #3 @ 1 unaligned?
29 mov r3, r1
44 stmiage ip!, {r1, r3, r8, lr}
45 stmiage ip!, {r1, r3, r8, lr}
46 stmiage ip!, {r1, r3, r8, lr}
53 stmiane ip!, {r1, r3, r8, lr}
54 stmiane ip!, {r1, r3, r8, lr}
89 stmiage ip!, {r1, r3-r8, lr}
103 stmiane ip!, {r1, r3}
119 cmp r3, #2 @ 1
[all …]
A Ddebug.S44 add r3, r2, r1
46 strb r1, [r3]
52 strb r1, [r3, #-1]!
53 teq r3, r2
66 addruart_current r3, r1, r2
68 1: waituart r2, r3
69 senduart r1, r3
70 busyuart r2, r3
82 addruart_current r3, r1, r2
A Drelocate.S81 adr r3, relocate_base
83 add r1, r3 /* r1 <- Run &__image_copy_start */
87 add r2, r3 /* r2 <- Run &__image_copy_end */
98 add r2, r1, r3 /* r2 <- Run &__rel_dyn_start */
100 add r3, r1, r3 /* r3 <- Run &__rel_dyn_end */
113 cmp r2, r3
A Dashldi3.S21 subs r3, r2, #32
24 movpl ah, al, lsl r3
26 THUMB( lsrmi r3, al, ip )
27 THUMB( orrmi ah, ah, r3 )
A Dashrdi3.S21 subs r3, r2, #32
24 movpl al, ah, asr r3
26 THUMB( lslmi r3, ah, ip )
27 THUMB( orrmi al, al, r3 )
A Dlshrdi3.S21 subs r3, r2, #32
24 movpl al, ah, lsr r3
26 THUMB( lslmi r3, ah, ip )
27 THUMB( orrmi al, al, r3 )
A Dmemcpy.S79 CALGN( rsb r3, ip, #32 )
112 ldr1w r1, r3, abort=20f
130 str1w r0, r3, abort=20f
143 ldr1b r1, r3, ne, abort=21f
146 str1b r0, r3, ne, abort=21f
155 ldr1b r1, r3, gt, abort=21f
158 str1b r0, r3, gt, abort=21f
195 mov r3, lr, lspull #\pull
198 orr r3, r3, r4, lspush #\push
226 orr r3, r3, lr, lspush #\push
[all …]
A Dbitops.S20 rsb r3, r0, #0
21 and r0, r0, r3
39 rsb r3, r0, #0
40 and r0, r0, r3
/arch/arm/include/asm/arch-rk3066/
A Dboot0.h27 ldr r3, =CONFIG_ROCKCHIP_BOOT_LR_REG
28 cmp lr, r3 /* if (LR != CONFIG_ROCKCHIP_BOOT_LR_REG) */
39 ldr r3, =CONFIG_ROCKCHIP_BOOT_MODE_REG
40 ldr r0, [r3] /* if (readl(CONFIG_ROCKCHIP_BOOT_MODE_REG) != */
45 str r0, [r3] /* writel(0, CONFIG_ROCKCHIP_BOOT_MODE_REG); */
47 ldr r3, =CONFIG_ROCKCHIP_BOOT_RETURN_REG
48 bx r3 /* return to CONFIG_ROCKCHIP_BOOT_RETURN_REG;*/
/arch/arm/mach-imx/mx7/
A Dpsci-suspend.S27 and r3, r1, r0, lsr #3 @ NumWays - 1
33 clz r1, r3 @ WayShift
34 add r4, r3, #1 @ NumWays
37 mov r3, r4 @ Temp = NumWays
39 subs r3, r3, #1 @ Temp--
40 mov r5, r3, lsl r1
/arch/sh/include/asm/
A Dmacro.h29 mov.l \time ,r3
32 tst r3, r3
34 dt r3

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