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Searched refs:rank (Results 1 – 24 of 24) sorted by relevance

/arch/x86/cpu/quark/
A Dmrc_util.h87 void set_rcvn(uint8_t channel, uint8_t rank,
90 void set_rdqs(uint8_t channel, uint8_t rank,
93 void set_wdqs(uint8_t channel, uint8_t rank,
96 void set_wdq(uint8_t channel, uint8_t rank,
101 void set_wclk(uint8_t channel, uint8_t rank, uint32_t pi_count);
102 uint32_t get_wclk(uint8_t channel, uint8_t rank);
103 void set_wctl(uint8_t channel, uint8_t rank, uint32_t pi_count);
104 uint32_t get_wctl(uint8_t channel, uint8_t rank);
108 uint32_t get_addr(uint8_t channel, uint8_t rank);
110 uint8_t rank, bool rcvn);
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A Dmrc_util.c790 temp >>= rank ? 12 : 8; in get_wclk()
804 temp >>= rank ? 16 : 8; in get_wclk()
1005 if (rank > 1) { in get_addr()
1125 channel, rank, rcvn); in find_rising_edge()
1213 set_rcvn(channel, rank, in find_rising_edge()
1216 set_wdqs(channel, rank, in find_rising_edge()
1230 set_rcvn(channel, rank, in find_rising_edge()
1448 uint8_t rank; in print_timings() local
1458 for (rank = 0; rank < NUM_RANKS; rank++) { in print_timings()
1460 (1 << rank)) { in print_timings()
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A Dsmc.c1150 uint8_t twr, wl, rank; in perform_jedec_init() local
1190 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
1195 dram_init_command(DCMD_NOP(rank)); in perform_jedec_init()
1299 for (rank = 0; rank < NUM_RANKS; rank++) { in perform_jedec_init()
1304 emrs2_cmd |= (rank << 22); in perform_jedec_init()
1307 emrs3_cmd |= (rank << 22); in perform_jedec_init()
1310 emrs1_cmd |= (rank << 22); in perform_jedec_init()
1313 mrs0_cmd |= (rank << 22); in perform_jedec_init()
1316 dram_init_command(DCMD_ZQCL(rank)); in perform_jedec_init()
2482 uint32_t rank; in set_auto_refresh() local
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/arch/arm/mach-uniphier/dram/
A Dcmd_ddrphy.c143 int rank; in __wld_dump() local
147 for (rank = 0; rank < 4; rank++) { in __wld_dump()
148 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
149 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
166 int rank; in __dqsgd_dump() local
170 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
171 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
172 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
A Dcmd_ddrmphy.c169 int rank; in __wld_dump() local
173 for (rank = 0; rank < 4; rank++) { in __wld_dump()
174 u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */ in __wld_dump()
175 u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */ in __wld_dump()
192 int rank; in __dqsgd_dump() local
196 for (rank = 0; rank < 4; rank++) { in __dqsgd_dump()
197 u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */ in __dqsgd_dump()
198 u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */ in __dqsgd_dump()
A Dddrphy-training.c21 void ddrphy_prepare_training(void __iomem *phy_base, int rank) in ddrphy_prepare_training() argument
31 tmp |= (1 << (PHY_DX_GCR_WLRKEN_SHIFT + rank)) & in ddrphy_prepare_training()
40 tmp |= (rank << PHY_DTCR_DTRANK_SHIFT) & PHY_DTCR_DTRANK_MASK; in ddrphy_prepare_training()
45 tmp |= (1 << (PHY_DTCR_RANKEN_SHIFT + rank)) & PHY_DTCR_RANKEN_MASK; in ddrphy_prepare_training()
A Dddrphy-init.h13 void ddrphy_prepare_training(void __iomem *phy_base, int rank);
A Dumc-pxs2.c120 int dx, rank; in ddrphy_get_system_latency() local
126 for (rank = 0; rank < 4; rank++) { in ddrphy_get_system_latency()
/arch/arm/mach-sunxi/
A Ddram_sunxi_dw.c656 rank->page_size = 512; in mctl_auto_detect_dram_size_rank()
657 rank->row_bits = 16; in mctl_auto_detect_dram_size_rank()
658 rank->bank_bits = 2; in mctl_auto_detect_dram_size_rank()
661 for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++) in mctl_auto_detect_dram_size_rank()
662 if (mctl_mem_matches_base((1 << (rank->row_bits + rank->bank_bits)) * rank->page_size, base)) in mctl_auto_detect_dram_size_rank()
666 rank->bank_bits = 3; in mctl_auto_detect_dram_size_rank()
669 for (rank->bank_bits = 2; rank->bank_bits < 3; rank->bank_bits++) in mctl_auto_detect_dram_size_rank()
670 if (mctl_mem_matches_base((1 << rank->bank_bits) * rank->page_size, base)) in mctl_auto_detect_dram_size_rank()
674 rank->page_size = 8192; in mctl_auto_detect_dram_size_rank()
677 for (rank->page_size = 512; rank->page_size < 8192; rank->page_size *= 2) in mctl_auto_detect_dram_size_rank()
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A Ddram_sun8i_a33.c27 u8 rank; member
43 MCTL_CR_BANK(para->bank) | MCTL_CR_RANK(para->rank), in mctl_set_cr()
49 u8 orig_rank = para->rank; in auto_detect_dram_size()
56 para->rank = 1; in auto_detect_dram_size()
73 para->rank = orig_rank; in auto_detect_dram_size()
185 if (para->rank == 2) in mctl_data_train_cfg()
233 para->rank = 2; in mctl_channel_init()
260 para->rank = 1; in mctl_channel_init()
338 .rank = 2, in sunxi_dram_init()
355 if (para.rank == 2) in sunxi_dram_init()
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A Ddram_sun8i_a83t.c25 u8 rank; member
48 u8 orig_rank = para->rank; in auto_detect_dram_size()
55 para->rank = 1; in auto_detect_dram_size()
72 para->rank = orig_rank; in auto_detect_dram_size()
217 if (para->rank == 2) in mctl_data_train_cfg()
315 para->rank = 2; in mctl_channel_init()
351 para->rank = 1; in mctl_channel_init()
415 para->rank = 2; in mctl_sys_init()
435 .rank = 1, in sunxi_dram_init()
464 if (para.rank == 2) in sunxi_dram_init()
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A Ddram_sun6i.c25 u8 rank; member
92 static bool mctl_rank_detect(u32 *gsr0, int rank) in mctl_rank_detect() argument
94 const u32 done = MCTL_DX_GSR0_RANK0_TRAIN_DONE << rank; in mctl_rank_detect()
95 const u32 err = MCTL_DX_GSR0_RANK0_TRAIN_ERR << rank; in mctl_rank_detect()
167 para->rank = 1; in mctl_channel_init()
275 MCTL_CR_BANK(1) | MCTL_CR_RANK(para->rank), &mctl_com->cr); in mctl_com_init()
340 .rank = 2, in sunxi_dram_init()
408 MCTL_CR_RANK(para.rank)); in sunxi_dram_init()
410 return 1 << (para.rank + para.rows + bank + columns + para.chan + bus); in sunxi_dram_init()
A Ddram_sun4i.c366 static void mctl_set_dqs_gating_delay(int rank, u32 dqs_gating_delay) in mctl_set_dqs_gating_delay() argument
371 u32 slr = readl(rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()
373 u32 dgr = readl(rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()
381 writel(slr, rank == 0 ? &dram->rslr0 : &dram->rslr1); in mctl_set_dqs_gating_delay()
382 writel(dgr, rank == 0 ? &dram->rdgr0 : &dram->rdgr1); in mctl_set_dqs_gating_delay()
A Ddram_sun9i.c101 u8 rank; member
349 | MCTL_CR_PAGE_SIZE(para->page_size) | MCTL_CR_RANK(para->rank), in mctl_com_init()
594 MCTL_MSTR_ACTIVERANKS(para->rank) | in mctl_channel_init()
688 writel(MCTL_DTCR_DEFAULT | MCTL_DTCR_RANKEN(para->rank), in mctl_channel_init()
872 .rank = 1, in sunxi_dram_init()
/arch/arm/include/asm/arch-rockchip/
A Dsdram_pctl_px30.h224 void pctl_read_mr(void __iomem *pctl_base, u32 rank, u32 mr_num);
225 int pctl_write_mr(void __iomem *pctl_base, u32 rank, u32 mr_num, u32 arg,
227 int pctl_write_vrefdq(void __iomem *pctl_base, u32 rank, u32 vrefrate,
A Dsdram_rk3288.h17 u8 rank; member
A Dsdram_common.h223 unsigned int rank; member
A Dsdram_rk3036.h318 u32 rank; member
A Dsdram_rk322x.h18 u8 rank; member
/arch/arm/mach-rockchip/rk3036/
A Dsdram_rk3036.c444 u32 rank, u32 cmd, u32 arg) in send_command() argument
446 writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); in send_command()
655 if (config.rank == 2) { in dram_cfg_rbc()
704 if (config.rank > 1) in sdram_all_config()
709 (config.rank - 1) << DDR_RANK_CNT_SHIFT | in sdram_all_config()
721 u32 size, os_reg, cs0_row, cs1_row, col, bank, rank; in sdram_size() local
730 rank = 1 + ((os_reg >> DDR_RANK_CNT_SHIFT) & DDR_RANK_CNT_MASK); in sdram_size()
735 if (rank > 1) in sdram_size()
/arch/arm/mach-rockchip/
A Dsdram.c350 u32 rank, cs0_col, bk, cs0_row, cs1_row, bw, row_3_4; in rockchip_sdram_size() local
371 rank = 1 + (sys_reg2 >> SYS_REG_RANK_SHIFT(ch) & in rockchip_sdram_size()
428 if (rank > 1) in rockchip_sdram_size()
434 if (rank > 1) in rockchip_sdram_size()
437 rank, cs0_col, cs1_col, bk, cs0_row, in rockchip_sdram_size()
442 rank, cs0_col, bk, cs0_row, in rockchip_sdram_size()
/arch/arm/mach-keystone/
A Dddr3_spd.c136 u8 rank; member
179 spd->rank = ((buf->organization & 0x38) >> 3) + 1; in ddrtimingcalculation()
180 if (spd->rank > 2) in ddrtimingcalculation()
359 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7; in init_ddr3param()
375 if (spd->rank == 2) in init_ddr3param()
401 spd_cb->emif_cfg.zqcfg = (spd->rank == 2) ? 0xF0073200 : 0x70073200; in init_ddr3param()
/arch/x86/dts/
A Dgalileo.dts51 rank-mask = <DRAM_RANK(0)>;
A Dchromebook_coral.dts711 fspm,dual-rank-support-enable = <1>;
713 fspm,ch0-rank-enable = <1>;
719 fspm,ch1-rank-enable = <1>;
725 fspm,ch2-rank-enable = <1>;
731 fspm,ch3-rank-enable = <1>;

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