Home
last modified time | relevance | path

Searched refs:rate (Results 1 – 25 of 170) sorted by relevance

1234567

/arch/arm/mach-imx/mx7ulp/
A Dscg.c211 rate = rate / val * 18; in scg_apll_pfd_get_rate()
261 rate = rate / val * 18; in scg_spll_pfd_get_rate()
281 rate = rate / (val + 1); in scg_apll_get_rate()
285 rate = rate / (val + 1); in scg_apll_get_rate()
311 rate = rate / (val + 1); in scg_spll_get_rate()
315 rate = rate / (val + 1); in scg_spll_get_rate()
374 rate = rate / (val + 1); in scg_nic_get_rate()
397 rate = rate / (val + 1); in scg_nic_get_rate()
425 rate = rate / (val + 1); in scg_nic_get_rate()
468 rate = rate / (val + 1); in scg_sys_get_rate()
[all …]
/arch/arm/mach-socfpga/
A Dclock_manager_agilex5.c32 ulong rate; in cm_get_rate_dm() local
46 rate = clk_get_rate(&clk); in cm_get_rate_dm()
48 if ((rate == (unsigned long)-ENOSYS) || in cm_get_rate_dm()
49 (rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
50 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
52 __func__, id, rate); in cm_get_rate_dm()
56 return rate; in cm_get_rate_dm()
A Dclock_manager_agilex.c23 ulong rate; in cm_get_rate_dm() local
37 rate = clk_get_rate(&clk); in cm_get_rate_dm()
39 if ((rate == (unsigned long)-ENOSYS) || in cm_get_rate_dm()
40 (rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
41 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
43 __func__, id, rate); in cm_get_rate_dm()
47 return rate; in cm_get_rate_dm()
A Dclock_manager_n5x.c22 ulong rate; in cm_get_rate_dm() local
36 rate = clk_get_rate(&clk); in cm_get_rate_dm()
38 if ((rate == (unsigned long)-ENXIO) || in cm_get_rate_dm()
39 (rate == (unsigned long)-EIO)) { in cm_get_rate_dm()
41 __func__, id, rate); in cm_get_rate_dm()
45 return rate; in cm_get_rate_dm()
/arch/arm/mach-nexell/
A Dclock.c527 return rate; in core_get_rate()
532 return clk->rate; in core_set_rate()
557 return rate; in clk_divide()
570 ret = rate / div; in clk_divide()
650 rate = pll->clk.rate; in clk_round_rate()
653 if (!rate) in clk_round_rate()
657 rate = clk_divide(rate, request, 2, &div[i]); in clk_round_rate()
673 rate_hz = rate; in clk_round_rate()
697 rate); in clk_round_rate()
702 return clk->rate; in clk_round_rate()
[all …]
/arch/mips/mach-pic32/
A Dcpu.c28 static ulong rate(int id) in rate() function
50 return rate(PB7CLK); in clk_get_cpu_rate()
59 ulong rate; in prefetch_init() local
62 rate = clk_get_cpu_rate() / 1000000; in prefetch_init()
69 if (rate < 66) in prefetch_init()
71 else if (rate < 133) in prefetch_init()
76 if (rate <= 83) in prefetch_init()
78 else if (rate <= 166) in prefetch_init()
/arch/arm/cpu/armv7/bcm235xx/
A Dclk-core.c171 diff = rate; in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
193 c->rate = new_rate; in peri_clk_set_rate()
199 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
241 c->rate = c->parent->rate / c->div; in peri_clk_get_rate()
243 c->parent->rate, div, c->sel, c->rate); in peri_clk_get_rate()
245 return c->rate; in peri_clk_get_rate()
324 return c->rate; in ccu_clk_get_rate()
384 return c->rate; in bus_clk_get_rate()
479 unsigned long rate; in clk_get_rate() local
[all …]
A Dclk-sdio.c13 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) in clk_sdio_enable() argument
58 ret = clk_set_rate(c, rate); in clk_sdio_enable()
69 *actual_ratep = rate; in clk_sdio_enable()
/arch/arm/cpu/armv7/bcm281xx/
A Dclk-core.c171 diff = rate; in peri_clk_set_rate()
182 div = ref->clk.rate / rate; in peri_clk_set_rate()
193 c->rate = new_rate; in peri_clk_set_rate()
199 c->name, c->rate, c->div, c->sel, c->parent->rate); in peri_clk_set_rate()
241 c->rate = c->parent->rate / c->div; in peri_clk_get_rate()
243 c->parent->rate, div, c->sel, c->rate); in peri_clk_get_rate()
245 return c->rate; in peri_clk_get_rate()
324 return c->rate; in ccu_clk_get_rate()
384 return c->rate; in bus_clk_get_rate()
479 unsigned long rate; in clk_get_rate() local
[all …]
A Dclk-sdio.c13 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep) in clk_sdio_enable() argument
58 ret = clk_set_rate(c, rate); in clk_sdio_enable()
69 *actual_ratep = rate; in clk_sdio_enable()
/arch/arm/mach-tegra/
A Demc.c25 unsigned rate; in board_emc_init() local
30 rate = EMC_SDRAM_RATE_T20; in board_emc_init()
33 rate = EMC_SDRAM_RATE_T25; in board_emc_init()
36 return tegra_set_emc(gd->fdt_blob, rate); in board_emc_init()
A Dclock.c255 unsigned long rate) in clk_get_divider() argument
260 divider += rate - 1; in clk_get_divider()
261 do_div(divider, rate); in clk_get_divider()
311 u64 rate; in get_rate_from_divider() local
315 return rate; in get_rate_from_divider()
389 int best_error = rate; in find_best_divider()
395 rate); in find_best_divider()
479 rate, &xdiv); in clock_adjust_periph_pll_div()
565 u64 parent_rate, rate; in clock_get_rate() local
606 do_div(rate, divm); in clock_get_rate()
[all …]
/arch/arm/mach-zynq/
A Dclk.c25 ulong rate; in set_cpu_clk_info() local
39 rate = clk_get_rate(&clk) / 1000000; in set_cpu_clk_info()
41 gd->bd->bi_ddr_freq = rate; in set_cpu_clk_info()
43 gd->bd->bi_arm_freq = rate; in set_cpu_clk_info()
/arch/arm/mach-tegra/tegra20/
A Demc.c173 static int decode_emc(const void *blob, unsigned rate, struct emc_ctlr **emcp, in decode_emc() argument
188 rate = rate / 2 / 1000; in decode_emc()
220 if (node_rate == rate) in decode_emc()
225 rate); in decode_emc()
241 int tegra_set_emc(const void *blob, unsigned rate) in tegra_set_emc() argument
247 err = decode_emc(blob, rate, &emc, &table); in tegra_set_emc()
/arch/arm/mach-nexell/include/mach/
A Dclk.h11 unsigned long rate; member
19 long clk_round_rate(struct clk *clk, unsigned long rate);
20 int clk_set_rate(struct clk *clk, unsigned long rate);
/arch/arm/dts/
A Dzynqmp-zc1751-xm019-dc5.dts123 slew-rate = <SLEW_RATE_SLOW>;
136 slew-rate = <SLEW_RATE_SLOW>;
150 slew-rate = <SLEW_RATE_SLOW>;
163 slew-rate = <SLEW_RATE_SLOW>;
176 slew-rate = <SLEW_RATE_SLOW>;
199 slew-rate = <SLEW_RATE_SLOW>;
222 slew-rate = <SLEW_RATE_SLOW>;
247 slew-rate = <SLEW_RATE_SLOW>;
261 slew-rate = <SLEW_RATE_SLOW>;
275 slew-rate = <SLEW_RATE_SLOW>;
[all …]
A Dzynqmp-zc1751-xm015-dc1.dts146 slew-rate = <SLEW_RATE_SLOW>;
159 slew-rate = <SLEW_RATE_SLOW>;
172 slew-rate = <SLEW_RATE_SLOW>;
202 slew-rate = <SLEW_RATE_FAST>;
210 slew-rate = <SLEW_RATE_SLOW>;
222 slew-rate = <SLEW_RATE_SLOW>;
247 slew-rate = <SLEW_RATE_SLOW>;
261 slew-rate = <SLEW_RATE_SLOW>;
275 slew-rate = <SLEW_RATE_SLOW>;
288 slew-rate = <SLEW_RATE_SLOW>;
[all …]
A Dzynq-zc702.dts204 slew-rate = <0>;
227 slew-rate = <0>;
250 slew-rate = <0>;
268 slew-rate = <0>;
292 slew-rate = <0>;
305 slew-rate = <0>;
318 slew-rate = <0>;
332 slew-rate = <0>;
345 slew-rate = <0>;
358 slew-rate = <0>;
[all …]
A Dzynqmp-sck-kd-g-revA.dtso176 slew-rate = <SLEW_RATE_SLOW>;
195 slew-rate = <SLEW_RATE_SLOW>;
219 slew-rate = <SLEW_RATE_SLOW>;
245 slew-rate = <SLEW_RATE_SLOW>;
258 slew-rate = <SLEW_RATE_SLOW>;
271 slew-rate = <SLEW_RATE_SLOW>;
298 slew-rate = <SLEW_RATE_SLOW>;
325 slew-rate = <SLEW_RATE_FAST>;
334 slew-rate = <SLEW_RATE_SLOW>;
353 slew-rate = <SLEW_RATE_FAST>;
[all …]
/arch/arm/include/asm/kona-common/
A Dclk.h21 long clk_round_rate(struct clk *clk, unsigned long rate);
22 int clk_set_rate(struct clk *clk, unsigned long rate);
25 int clk_sdio_enable(void *base, u32 rate, u32 *actual_ratep);
/arch/arm/mach-imx/imx8ulp/
A Dcgc.c367 u32 reg, rate; in cgc2_nic_get_rate() local
381 rate = rate / lpav_axi_clk; in cgc2_nic_get_rate()
384 rate = rate / (lpav_axi_clk * lpav_ahb_clk); in cgc2_nic_get_rate()
387 rate = rate / (lpav_axi_clk * lpav_bus_clk); in cgc2_nic_get_rate()
393 return rate; in cgc2_nic_get_rate()
576 u32 reg, rate; in cgc1_nic_get_rate() local
595 rate = rate / nic_ad_divplat; in cgc1_nic_get_rate()
598 rate = rate / (nic_ad_divplat * nic_per_divplat); in cgc1_nic_get_rate()
601 rate = rate / (nic_ad_divplat * xbar_ad_divplat); in cgc1_nic_get_rate()
607 rate = rate / (nic_ad_divplat * xbar_ad_divplat * ad_slow); in cgc1_nic_get_rate()
[all …]
/arch/riscv/dts/
A Dth1520-lichee-module-4a.dtsi86 slew-rate = <0>;
101 slew-rate = <0>;
118 slew-rate = <0>;
133 slew-rate = <0>;
145 slew-rate = <0>;
155 slew-rate = <0>;
/arch/mips/mach-octeon/
A Dcvmx-helper-sfp.c227 sfp_info->rate = CVMX_SFP_RATE_1G; in cvmx_sfp_parse_sfp_buffer()
259 sfp_info->rate = CVMX_SFP_RATE_40G; in cvmx_sfp_parse_sfp_buffer()
261 sfp_info->rate = CVMX_SFP_RATE_25G; in cvmx_sfp_parse_sfp_buffer()
265 sfp_info->rate = CVMX_SFP_RATE_10G; in cvmx_sfp_parse_sfp_buffer()
267 sfp_info->rate = CVMX_SFP_RATE_1G; in cvmx_sfp_parse_sfp_buffer()
294 sfp_info->rate = CVMX_SFP_RATE_25G; in cvmx_sfp_parse_sfp_buffer()
300 sfp_info->rate = CVMX_SFP_RATE_40G; in cvmx_sfp_parse_sfp_buffer()
309 sfp_info->rate = CVMX_SFP_RATE_10G; in cvmx_sfp_parse_sfp_buffer()
460 sfp_info->rate = CVMX_SFP_RATE_1G; in cvmx_sfp_parse_qsfp_buffer()
485 sfp_info->rate = CVMX_SFP_RATE_1G; in cvmx_sfp_parse_qsfp_buffer()
[all …]
/arch/arm/include/asm/arch-rockchip/
A Dclock.h72 .rate = _rate##U, \
83 .rate = _rate##U, \
91 unsigned long rate; member
132 unsigned long rate; member
144 ulong rate);
/arch/arm/cpu/arm926ejs/mxs/
A Dclock.c278 uint32_t divide, rate, tgtclk; in mxs_set_ssp_busclock() local
288 rate = sspclk / freq / divide; in mxs_set_ssp_busclock()
289 if (rate <= 256) in mxs_set_ssp_busclock()
293 tgtclk = sspclk / divide / rate; in mxs_set_ssp_busclock()
295 rate++; in mxs_set_ssp_busclock()
296 tgtclk = sspclk / divide / rate; in mxs_set_ssp_busclock()
298 if (rate > 256) in mxs_set_ssp_busclock()
299 rate = 256; in mxs_set_ssp_busclock()
304 ((rate - 1) << SSP_TIMING_CLOCK_RATE_OFFSET); in mxs_set_ssp_busclock()

Completed in 51 milliseconds

1234567