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Searched refs:reg_val (Results 1 – 16 of 16) sorted by relevance

/arch/arm/mach-sunxi/
A Ddram_sun4i.c67 u32 reg_val; in mctl_ddr3_reset() local
70 reg_val = readl(&timer->cpu_cfg); in mctl_ddr3_reset()
240 u32 reg_val; in mctl_setup_dram_clock() local
254 reg_val |= CCM_PLL5_CTRL_P(1); in mctl_setup_dram_clock()
388 u32 reg_val; in dramc_scan_readpipe() local
398 reg_val = readl(&dram->csr); in dramc_scan_readpipe()
514 u32 reg_val; in mctl_set_impedance() local
565 u32 reg_val; in dramc_init_helper() local
596 reg_val = DRAM_DCR_TYPE_DDR3; in dramc_init_helper()
619 writel(reg_val, &dram->dcr); in dramc_init_helper()
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A Dcpu_info.c128 uint32_t reg_val; in sun8i_efuse_read() local
130 reg_val = readl(SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
131 reg_val &= ~(((0x1ff) << 16) | 0x3); in sun8i_efuse_read()
132 reg_val |= (offset << 16); in sun8i_efuse_read()
133 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
135 reg_val &= ~(((0xff) << 8) | 0x3); in sun8i_efuse_read()
136 reg_val |= (SIDC_OP_LOCK << 8) | 0x2; in sun8i_efuse_read()
137 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
142 writel(reg_val, SUNXI_SIDC_BASE + SIDC_PRCTL); in sun8i_efuse_read()
144 reg_val = readl(SUNXI_SIDC_BASE + SIDC_RDKEY); in sun8i_efuse_read()
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A Ddram_sun8i_a33.c91 u32 reg_val; in auto_set_timing_para() local
140 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
142 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
144 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
146 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
153 reg_val &= ~(0xff << 8); in auto_set_timing_para()
154 reg_val &= ~(0xff << 0); in auto_set_timing_para()
155 reg_val |= (0x33 << 8); in auto_set_timing_para()
156 reg_val |= (0x10 << 0); in auto_set_timing_para()
162 writel(reg_val, &mctl_ctl->pitmg0); in auto_set_timing_para()
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A Ddram_sun8i_a83t.c91 u32 reg_val; in auto_set_timing_para() local
172 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
174 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
176 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
178 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
185 reg_val &= ~(0xff << 8); in auto_set_timing_para()
186 reg_val &= ~(0xff << 0); in auto_set_timing_para()
187 reg_val |= (0x33 << 8); in auto_set_timing_para()
188 reg_val |= (0x8 << 0); in auto_set_timing_para()
194 writel(reg_val, &mctl_ctl->pitmg0); in auto_set_timing_para()
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A Ddram_sun50i_h6.c298 u32 reg_val, tmp; in mctl_com_init() local
311 reg_val = 0xf00; in mctl_com_init()
313 reg_val = 0x1f00; in mctl_com_init()
315 reg_val = 0x3f00; in mctl_com_init()
321 reg_val |= MSTR_DEVICETYPE_LPDDR3; in mctl_com_init()
325 reg_val |= MSTR_BUSWIDTH_FULL; in mctl_com_init()
327 reg_val |= MSTR_BUSWIDTH_HALF; in mctl_com_init()
331 reg_val = DCR_LPDDR3 | DCR_DDR8BANK; in mctl_com_init()
344 reg_val = 0x0400; in mctl_com_init()
345 reg_val |= (tmp + 7) << 24; in mctl_com_init()
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A Ddram_sunxi_dw.c310 u32 reg_val; in mctl_h3_zq_calibration_quirk() local
318 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_h3_zq_calibration_quirk()
320 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
325 reg_val |= reg_val << 8; in mctl_h3_zq_calibration_quirk()
368 u32 reg_val; in mctl_v3s_zq_calibration_quirk() local
374 reg_val = readl(&mctl_ctl->zqdr[0]); in mctl_v3s_zq_calibration_quirk()
376 reg_val |= reg_val << 8; in mctl_v3s_zq_calibration_quirk()
377 writel(reg_val, &mctl_ctl->zqdr[0]); in mctl_v3s_zq_calibration_quirk()
379 reg_val = readl(&mctl_ctl->zqdr[1]); in mctl_v3s_zq_calibration_quirk()
381 reg_val |= reg_val << 8; in mctl_v3s_zq_calibration_quirk()
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A Ddram_sun50i_h616.c1207 u32 reg_val; in mctl_ctrl_init() local
1222 reg_val = MSTR_ACTIVE_RANKS(config->ranks); in mctl_ctrl_init()
1238 reg_val |= MSTR_BUSWIDTH_FULL; in mctl_ctrl_init()
1240 reg_val |= MSTR_BUSWIDTH_HALF; in mctl_ctrl_init()
1250 reg_val = 0x06000400; in mctl_ctrl_init()
1253 reg_val = 0x09020400; in mctl_ctrl_init()
1256 reg_val = 0x04000400; in mctl_ctrl_init()
1262 writel(reg_val, &mctl_ctl->odtcfg); in mctl_ctrl_init()
1263 writel(reg_val, &mctl_ctl->unk_0x2240); in mctl_ctrl_init()
1264 writel(reg_val, &mctl_ctl->unk_0x3240); in mctl_ctrl_init()
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A Ddram_sun9i.c828 unsigned int reg_val; in DRAMC_get_dram_size() local
832 reg_val = readl(&mctl_com->cr); in DRAMC_get_dram_size()
834 temp = (reg_val >> 8) & 0xf; /* page size code */ in DRAMC_get_dram_size()
837 temp = (reg_val >> 4) & 0xf; /* row width code */ in DRAMC_get_dram_size()
840 temp = (reg_val >> 2) & 0x3; /* bank number code */ in DRAMC_get_dram_size()
843 temp = reg_val & 0x3; /* rank number code */ in DRAMC_get_dram_size()
846 temp = (reg_val >> 19) & 0x1; /* channel number code */ in DRAMC_get_dram_size()
A Ddram_sun55i_a523.c1299 u32 reg_val; in mctl_ctrl_init() local
1316 reg_val = MSTR_ACTIVE_RANKS(config->ranks); in mctl_ctrl_init()
1328 reg_val |= MSTR_BUSWIDTH_FULL; in mctl_ctrl_init()
1330 reg_val |= MSTR_BUSWIDTH_HALF; in mctl_ctrl_init()
1331 writel(BIT(31) | BIT(30) | reg_val, &mctl_ctl->mstr); in mctl_ctrl_init()
1340 reg_val = 0x06000400; in mctl_ctrl_init()
1343 reg_val = 0x04000400; in mctl_ctrl_init()
1348 writel(reg_val, &mctl_ctl->odtcfg); in mctl_ctrl_init()
1349 writel(reg_val, &mctl_ctl->unk_0x2240); in mctl_ctrl_init()
1350 writel(reg_val, &mctl_ctl->unk_0x3240); in mctl_ctrl_init()
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/arch/arm/mach-imx/mx7/
A Dddr.c139 u32 reg_val, field_val; in imx_ddr_size() local
143 reg_val = readl(&ddrc_regs->mstr); in imx_ddr_size()
152 reg_val = readl(&ddrc_regs->addrmap2); in imx_ddr_size()
153 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT; in imx_ddr_size()
156 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT; in imx_ddr_size()
159 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT; in imx_ddr_size()
165 reg_val = readl(&ddrc_regs->addrmap3); in imx_ddr_size()
178 reg_val = readl(&ddrc_regs->addrmap4); in imx_ddr_size()
186 reg_val = readl(&ddrc_regs->addrmap5); in imx_ddr_size()
199 reg_val = readl(&ddrc_regs->addrmap6); in imx_ddr_size()
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/arch/arm/mach-omap2/
A Dvc.c101 u32 reg_val; in omap_vc_bypass_send_value() local
108 reg_val = sa << PRM_VC_VAL_BYPASS_SLAVEADDR_SHIFT | in omap_vc_bypass_send_value()
111 writel(reg_val, (*prcm)->prm_vc_val_bypass); in omap_vc_bypass_send_value()
114 writel(reg_val | PRM_VC_VAL_BYPASS_VALID_BIT, in omap_vc_bypass_send_value()
119 reg_val = readl((*prcm)->prm_vc_val_bypass) & in omap_vc_bypass_send_value()
121 if (!reg_val) in omap_vc_bypass_send_value()
/arch/arm/mach-mvebu/serdes/a38x/
A Dsys_env_lib.h113 #define REF_CLK_SELECTOR_VAL_PEX0(reg_val) (reg_val >> 2) & 0x1 argument
114 #define REF_CLK_SELECTOR_VAL_PEX1(reg_val) (reg_val >> 3) & 0x1 argument
115 #define REF_CLK_SELECTOR_VAL_PEX2(reg_val) (reg_val >> 30) & 0x1 argument
116 #define REF_CLK_SELECTOR_VAL_PEX3(reg_val) (reg_val >> 31) & 0x1 argument
117 #define REF_CLK_SELECTOR_VAL(reg_val) (reg_val & 0x1) argument
/arch/arm/mach-exynos/
A Dlowlevel_init.c71 uint32_t val, reg_val; in low_power_start() local
73 reg_val = readl(EXYNOS5420_SPARE_BASE); in low_power_start()
74 if (reg_val != CPU_RST_FLAG_VAL) { in low_power_start()
79 reg_val = readl(CFG_PHY_IRAM_BASE + 0x4); in low_power_start()
80 if (reg_val != (uint32_t)&low_power_start) { in low_power_start()
/arch/arm/mach-imx/imx8ulp/upower/
A Dupower_hal.c76 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val) in upower_pmic_i2c_write() argument
81 ret = upwr_xcp_i2c_access(0x32, 1, 1, reg_addr, reg_val, NULL); in upower_pmic_i2c_write()
94 debug("PMIC write reg[0x%x], val[0x%x]\n", reg_addr, reg_val); in upower_pmic_i2c_write()
99 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val) in upower_pmic_i2c_read() argument
104 if (!reg_val) in upower_pmic_i2c_read()
120 *reg_val = ret_val; in upower_pmic_i2c_read()
122 debug("PMIC read reg[0x%x], val[0x%x]\n", reg_addr, *reg_val); in upower_pmic_i2c_read()
/arch/arm/include/asm/arch-imx8ulp/
A Dupower.h12 int upower_pmic_i2c_write(u32 reg_addr, u32 reg_val);
13 int upower_pmic_i2c_read(u32 reg_addr, u32 *reg_val);
/arch/arm/mach-zynq/
A Dslcr.c126 u32 reg_val; in zynq_slcr_devcfg_disable() local
134 reg_val = readl(&slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()
135 reg_val &= ~0xF; in zynq_slcr_devcfg_disable()
136 writel(reg_val, &slcr_base->lvl_shftr_en); in zynq_slcr_devcfg_disable()

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