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Searched refs:regval (Results 1 – 10 of 10) sorted by relevance

/arch/arm/mach-omap2/omap3/
A Demif4.c67 unsigned int regval; in do_emif4_init() local
71 writel(regval, &emif4_base->ddr_phyctrl1); in do_emif4_init()
76 regval = readl(&emif4_base->sdram_iodft_tlgc); in do_emif4_init()
77 regval |= (1<<10); in do_emif4_init()
78 writel(regval, &emif4_base->sdram_iodft_tlgc); in do_emif4_init()
84 regval |= (1<<0); in do_emif4_init()
91 writel(regval, &emif4_base->sdram_time1); in do_emif4_init()
97 writel(regval, &emif4_base->sdram_time2); in do_emif4_init()
101 writel(regval, &emif4_base->sdram_time3); in do_emif4_init()
107 writel(regval, &emif4_base->sdram_pwr_mgmt); in do_emif4_init()
[all …]
/arch/arm/mach-mvebu/armada3700/
A Defuse.c29 u32 regval; in otp_read_parallel() local
32 regval = readl(base + OTP_CONTROL_OFF); in otp_read_parallel()
33 regval &= ~OTP_MODE_BIT; in otp_read_parallel()
34 writel(regval, base + OTP_CONTROL_OFF); in otp_read_parallel()
38 regval |= OTP_POR_B_BIT; in otp_read_parallel()
43 regval |= OTP_PTR_INC_BIT; in otp_read_parallel()
48 regval |= OTP_RPTR_RST_BIT; in otp_read_parallel()
52 regval &= ~OTP_RPTR_RST_BIT; in otp_read_parallel()
62 regval |= OTP_PRDT_BIT; in otp_read_parallel()
66 regval &= ~OTP_PRDT_BIT; in otp_read_parallel()
[all …]
A Dcpu.c430 u32 regval; in get_ref_clk() local
432 regval = (readl(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >> in get_ref_clk()
435 if (regval == MVEBU_XTAL_CLOCK_25MHZ) in get_ref_clk()
/arch/arm/mach-nexell/
A Dtieoff.c43 u32 regval; in nx_tieoff_set() local
60 regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb); in nx_tieoff_set()
61 tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval); in nx_tieoff_set()
65 regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) >> msb); in nx_tieoff_set()
66 tieoff_writetl(&nx_tieoff->tieoffreg[regindex + 1], regval); in nx_tieoff_set()
70 regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb); in nx_tieoff_set()
71 tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval); in nx_tieoff_set()
79 u32 regval; in nx_tieoff_get() local
95 regval >>= lsb; in nx_tieoff_get()
103 regval >>= lsb; in nx_tieoff_get()
[all …]
/arch/arm/mach-at91/armv7/
A Dclock.c199 u32 regval, status; in at91_enable_periph_generated_clk() local
214 regval = readl(&pmc->pcr); in at91_enable_periph_generated_clk()
215 regval &= ~AT91_PMC_PCR_GCKCSS; in at91_enable_periph_generated_clk()
216 regval &= ~AT91_PMC_PCR_GCKDIV; in at91_enable_periph_generated_clk()
220 regval |= AT91_PMC_PCR_GCKCSS_SLOW_CLK; in at91_enable_periph_generated_clk()
223 regval |= AT91_PMC_PCR_GCKCSS_MAIN_CLK; in at91_enable_periph_generated_clk()
232 regval |= AT91_PMC_PCR_GCKCSS_MCK_CLK; in at91_enable_periph_generated_clk()
242 regval |= AT91_PMC_PCR_CMD_WRITE | in at91_enable_periph_generated_clk()
246 writel(regval, &pmc->pcr); in at91_enable_periph_generated_clk()
262 u32 regval, clk_source, div; in at91_get_periph_generated_clk() local
[all …]
/arch/arm/mach-zynqmp/
A Dpsu_spl_init.c53 unsigned long regval = 0; in psu_mask_write() local
55 regval = readl(offset); in psu_mask_write()
56 regval &= ~(mask); in psu_mask_write()
57 regval |= (val & mask); in psu_mask_write()
58 writel(regval, offset); in psu_mask_write()
/arch/arm/mach-at91/
A Dclock.c22 u32 regval; in at91_periph_clk_enable() local
32 regval = AT91_PMC_PCR_EN | AT91_PMC_PCR_CMD_WRITE | id | div_value; in at91_periph_clk_enable()
34 writel(regval, &pmc->pcr); in at91_periph_clk_enable()
45 u32 regval; in at91_periph_clk_disable() local
50 regval = AT91_PMC_PCR_CMD_WRITE | id; in at91_periph_clk_disable()
52 writel(regval, &pmc->pcr); in at91_periph_clk_disable()
/arch/mips/mach-ath79/ar934x/
A Dclk.c233 static u32 ar934x_cpupll_to_hz(const u32 regval) in ar934x_cpupll_to_hz() argument
235 const u32 outdiv = (regval >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) & in ar934x_cpupll_to_hz()
237 const u32 refdiv = (regval >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & in ar934x_cpupll_to_hz()
239 const u32 nint = (regval >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) & in ar934x_cpupll_to_hz()
241 const u32 nfrac = (regval >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) & in ar934x_cpupll_to_hz()
248 static u32 ar934x_ddrpll_to_hz(const u32 regval) in ar934x_ddrpll_to_hz() argument
250 const u32 outdiv = (regval >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) & in ar934x_ddrpll_to_hz()
252 const u32 refdiv = (regval >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & in ar934x_ddrpll_to_hz()
254 const u32 nint = (regval >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) & in ar934x_ddrpll_to_hz()
256 const u32 nfrac = (regval >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) & in ar934x_ddrpll_to_hz()
/arch/arm/mach-omap2/am33xx/
A Dboard.c355 u32 regval; in uart_soft_reset() local
357 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
358 regval |= UART_RESET; in uart_soft_reset()
359 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
365 regval = readl(&uart_base->uartsyscfg); in uart_soft_reset()
366 regval |= UART_SMART_IDLE_EN; in uart_soft_reset()
367 writel(regval, &uart_base->uartsyscfg); in uart_soft_reset()
/arch/mips/mach-mtmips/
A Dddr_cal.c75 int maxval, int shift, u32 regval) in dqs_find_max() argument
81 dqsval = regval | (fieldval << shift); in dqs_find_max()
90 int minval, int shift, u32 regval) in dqs_find_min() argument
96 dqsval = regval | (fieldval << shift); in dqs_find_min()

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