| /arch/arm/dts/ |
| A D | t8103-pmgr.dtsi | 14 #reset-cells = <0>;
23 #reset-cells = <0>;
32 #reset-cells = <0>;
41 #reset-cells = <0>;
49 #reset-cells = <0>;
57 #reset-cells = <0>;
65 #reset-cells = <0>;
73 #reset-cells = <0>;
82 #reset-cells = <0>;
91 #reset-cells = <0>;
[all …]
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| A D | ast2600-u-boot.dtsi | 3 #include <dt-bindings/reset/ast2600-reset.h>
13 #reset-cells = <1>;
17 rst: reset-controller {
19 compatible = "aspeed,ast2600-reset";
21 #reset-cells = <1>;
30 #reset-cells = <1>;
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| A D | ast2500-u-boot.dtsi | 3 #include <dt-bindings/reset/ast2500-reset.h>
13 #reset-cells = <1>;
16 rst: reset-controller {
18 compatible = "aspeed,ast2500-reset";
19 #reset-cells = <1>;
27 #reset-cells = <1>;
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| A D | imx6q-bx50v3-uboot.dtsi | 41 * with the kernel and the kernel should not reset the PHY, since
46 phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
47 phy-reset-duration = <1>;
48 phy-reset-post-delay = <0>;
52 * PCIe reset is not done in the file shared with the kernel, since
55 * be reset by the kernel, so it may not reset PCIe via this GPIO.
58 reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>;
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| A D | bcm2711-rpi.dtsi | 4 #include <dt-bindings/reset/raspberrypi,firmware-reset.h>
34 reset: reset { label
35 compatible = "raspberrypi,firmware-reset";
36 #reset-cells = <1>;
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| A D | tegra20.dtsi | 19 reset-names = "host1x";
32 reset-names = "mpe";
41 reset-names = "vi";
50 reset-names = "epp";
59 reset-names = "isp";
68 reset-names = "2d";
76 reset-names = "3d";
87 reset-names = "dc";
104 reset-names = "dc";
195 #reset-cells = <1>;
[all …]
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| A D | imx8mp-icore-mx8mp-edimm2.2-u-boot.dtsi | 111 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
112 reset-delay-us = <15000>;
113 reset-post-delay-us = <100000>;
117 phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
118 phy-reset-duration = <15>;
119 phy-reset-post-delay = <100>;
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| A D | tegra30.dtsi | 110 reset-names = "mpe";
119 reset-names = "vi";
128 reset-names = "epp";
137 reset-names = "isp";
146 reset-names = "2d";
168 reset-names = "dc";
187 reset-names = "dc";
225 reset-names = "dsi";
239 reset-names = "dsi";
302 #reset-cells = <1>;
[all …]
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| A D | tegra114.dtsi | 20 reset-names = "host1x";
33 reset-names = "2d";
41 reset-names = "3d";
52 reset-names = "dc";
71 reset-names = "dc";
90 reset-names = "hdmi";
102 reset-names = "dsi";
118 reset-names = "dsi";
168 #reset-cells = <1>;
213 reset-names = "dma";
[all …]
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| A D | uniphier-pro4.dtsi | 254 mio_rst: reset-controller {
256 #reset-cells = <1>;
270 peri_rst: reset-controller {
272 #reset-cells = <1>;
327 cap-mmc-hw-reset;
495 sys_rst: reset-controller {
497 #reset-cells = <1>;
552 #reset-cells = <1>;
599 #reset-cells = <1>;
664 #reset-cells = <1>;
[all …]
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| A D | hi3798mv200.dtsi | 11 #include <dt-bindings/reset/ti-syscon.h>
92 crg: clock-reset-controller@8a22000 {
96 #reset-cells = <2>;
103 #reset-cells = <2>;
150 reset-names = "reset";
164 reset-names = "reset";
179 reset-names = "mac_core", "mac_ifc", "phy";
192 reset-names = "bus";
207 reset-names = "bus", "phy", "utmi";
221 reset-names = "reset";
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| A D | am335x-brxre1.dts | 286 ti,no-reset-on-init;
291 ti,no-reset-on-init;
296 ti,no-reset-on-init;
301 ti,no-reset-on-init;
306 ti,no-reset-on-init;
312 ti,no-reset-on-init;
318 ti,no-reset-on-init;
324 ti,no-reset-on-init;
330 ti,no-reset-on-init;
336 ti,no-reset-on-init;
[all …]
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| A D | mt7987-netsys-u-boot.dtsi | 8 #include <dt-bindings/reset/mt7988-reset.h>
19 reset-names = "fe";
32 reset-names = "fe";
46 reset-names = "fe";
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| A D | uniphier-pxs2.dtsi | 277 reset-names = "aio";
437 #reset-cells = <1>;
453 #reset-cells = <1>;
469 cap-mmc-hw-reset;
482 reset-names = "host";
572 #reset-cells = <1>;
592 reset-names = "ether";
629 reset-names = "link";
631 #reset-cells = <1>;
672 #reset-cells = <1>;
[all …]
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| A D | uniphier-pxs3.dtsi | 385 #reset-cells = <1>;
401 #reset-cells = <1>;
433 reset-names = "host";
552 #reset-cells = <1>;
576 reset-names = "ether";
597 reset-names = "ether";
636 #reset-cells = <1>;
677 #reset-cells = <1>;
718 #reset-cells = <1>;
821 #reset-cells = <1>;
[all …]
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| A D | tegra124.dtsi | 105 reset-names = "dc";
120 reset-names = "dc";
135 reset-names = "hdmi";
147 reset-names = "dsi";
163 reset-names = "dsi";
181 reset-names = "sor";
222 reset-names = "gpu";
257 #reset-cells = <1>;
334 reset-names = "dma";
417 reset-names = "pwm";
[all …]
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| A D | imx8mp-debix-model-a-u-boot.dtsi | 36 reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>;
37 reset-delay-us = <15000>;
38 reset-post-delay-us = <100000>;
42 phy-reset-gpios = <&gpio4 19 GPIO_ACTIVE_LOW>;
43 phy-reset-duration = <15>;
44 phy-reset-post-delay = <100>;
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| A D | hi3798cv200-u-boot.dtsi | 11 #include <dt-bindings/reset/ti-syscon.h>
14 rst: reset-controller@8a22000 {
15 compatible = "hisilicon,hi3798cv200-reset";
17 #reset-cells = <3>;
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| A D | meson-gxbb-wetek-play2-u-boot.dtsi | 10 snps,reset-gpio = <&gpio GPIOZ_14 0>;
11 snps,reset-delays-us = <0 10000 1000000>;
12 snps,reset-active-low;
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| A D | meson-gxbb-kii-pro-u-boot.dtsi | 10 snps,reset-gpio = <&gpio GPIOZ_14 0>;
11 snps,reset-delays-us = <0>, <10000>, <1000000>;
12 snps,reset-active-low;
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| A D | meson-gxbb-nanopi-k2-u-boot.dtsi | 10 snps,reset-gpio = <&gpio GPIOZ_14 0>;
11 snps,reset-delays-us = <0 10000 1000000>;
12 snps,reset-active-low;
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| /arch/arm/mach-omap2/omap3/ |
| A D | emac.c | 20 u32 reset; in cpu_eth_init() local
23 reset = readl(&am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
24 reset &= ~CPGMACSS_SW_RST; in cpu_eth_init()
25 writel(reset, &am35x_scm_general_regs->ip_sw_reset); in cpu_eth_init()
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| /arch/mips/dts/ |
| A D | mt7620.dtsi | 3 #include <dt-bindings/reset/mt7620-reset.h>
44 #reset-cells = <1>;
51 reset-names = "sysreset";
64 reset-names = "uartf";
81 reset-names = "uartl";
158 reset-names = "wdt";
166 reset-names = "pio";
181 reset-names = "pio";
196 reset-names = "pio";
211 reset-names = "pio";
[all …]
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| /arch/x86/dts/ |
| A D | reset.dtsi | 2 reset: reset { label
3 compatible = "x86,reset";
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| /arch/arm/mach-snapdragon/include/mach/ |
| A D | boot0.h | 35 bne reset
48 b reset
53 .quad reset /* el1_elr */
|