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Searched refs:rpu_base (Results 1 – 4 of 4) sorted by relevance

/arch/arm/mach-versal/
A Dmp.c31 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()
36 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()
39 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()
44 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()
52 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
63 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
/arch/arm/mach-zynqmp/
A Dmp.c70 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_halt_mode()
75 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_halt_mode()
79 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_halt_mode()
84 writel(tmp, &rpu_base->rpu1_cfg); in set_r5_halt_mode()
92 tmp = readl(&rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
103 writel(tmp, &rpu_base->rpu_glbl_ctrl); in set_r5_tcm_mode()
163 tmp = readl(&rpu_base->rpu_glbl_ctrl); in check_r5_mode()
206 tmp = readl(&rpu_base->rpu0_cfg); in set_r5_start()
211 writel(tmp, &rpu_base->rpu0_cfg); in set_r5_start()
213 tmp = readl(&rpu_base->rpu1_cfg); in set_r5_start()
[all …]
/arch/arm/mach-versal/include/mach/
A Dhardware.h57 #define rpu_base ((struct rpu_regs *)VERSAL_RPU_BASEADDR) macro
/arch/arm/mach-zynqmp/include/mach/
A Dhardware.h123 #define rpu_base ((struct rpu_regs *)ZYNQMP_RPU_BASEADDR) macro

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