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Searched refs:sclk_div_isp (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock.c406 div = sub_div = readl(&clk->sclk_div_isp); in exynos5_get_periph_rate()
1491 reg = &clk->sclk_div_isp; in exynos5_set_spi_clk()
1496 reg = &clk->sclk_div_isp; in exynos5_set_spi_clk()
A Dclock_init_exynos5.c766 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp); in exynos5250_system_clock_init()
/arch/arm/mach-exynos/include/mach/
A Dclock.h734 unsigned int sclk_div_isp; member

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