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Searched refs:set_pll (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos5.c626 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5250_system_clock_init()
633 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv); in exynos5250_system_clock_init()
640 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv); in exynos5250_system_clock_init()
647 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv); in exynos5250_system_clock_init()
655 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv); in exynos5250_system_clock_init()
663 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv); in exynos5250_system_clock_init()
819 val = set_pll(arm_clk_ratio->apll_mdiv, in exynos5420_system_clock_init()
837 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv); in exynos5420_system_clock_init()
847 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv); in exynos5420_system_clock_init()
854 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv); in exynos5420_system_clock_init()
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A Dexynos5_setup.h22 #define set_pll(mdiv, pdiv, sdiv) (1<<31 | mdiv<<16 | pdiv<<8 | sdiv) macro

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