| /arch/x86/lib/ |
| A D | div64.c | 19 u64 __ashldi3(u64 num, unsigned int shift) in __ashldi3() argument
24 if (shift >= 32) { in __ashldi3()
28 if (!shift) in __ashldi3()
31 (output.words.lower >> (32 - shift)); in __ashldi3()
32 output.words.lower = output.words.lower << shift; in __ashldi3()
37 u64 __lshrdi3(u64 num, unsigned int shift) in __lshrdi3() argument
42 if (shift >= 32) { in __lshrdi3()
46 if (!shift) in __lshrdi3()
48 output.words.lower = output.words.lower >> shift | in __lshrdi3()
49 (output.words.higher << (32 - shift)); in __lshrdi3()
[all …]
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| A D | pmu.c | 53 unsigned int shift = (lss * 2) % 32; in pmu_power_lss() local
67 ssc &= ~(0x3 << shift); /* D0 */ in pmu_power_lss()
69 ssc |= 0x3 << shift; /* D3hot */ in pmu_power_lss()
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| /arch/arm/mach-uniphier/bcu/ |
| A D | bcu-ld4.c | 17 int shift; in uniphier_ld4_bcu_init() local
26 shift = bd->dram_ch[0].size / 0x04000000 * 4; in uniphier_ld4_bcu_init()
27 writel(ch(shift), BCIPPCCHR2); /* 0x80000000-0x9fffffff */ in uniphier_ld4_bcu_init()
29 shift -= 32; in uniphier_ld4_bcu_init()
30 writel(ch(shift), BCIPPCCHR3); /* 0xa0000000-0xbfffffff */ in uniphier_ld4_bcu_init()
32 shift -= 32; in uniphier_ld4_bcu_init()
33 writel(ch(shift), BCIPPCCHR4); /* 0xc0000000-0xdfffffff */ in uniphier_ld4_bcu_init()
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| /arch/arm/dts/ |
| A D | omap3xxx-clocks.dtsi | 25 ti,bit-shift = <6>;
36 ti,bit-shift = <7>;
85 ti,bit-shift = <4>;
99 ti,bit-shift = <2>;
113 ti,bit-shift = <6>;
140 ti,bit-shift = <2>;
245 ti,bit-shift = <16>;
352 ti,bit-shift = <6>;
360 ti,bit-shift = <8>;
387 ti,bit-shift = <5>;
[all …]
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| A D | omap34xx-omap36xx-clocks.dtsi | 20 ti,bit-shift = <3>;
29 ti,bit-shift = <2>;
37 ti,bit-shift = <1>;
45 ti,bit-shift = <0>;
52 ti,bit-shift = <0>;
62 ti,bit-shift = <0>;
70 ti,bit-shift = <1>;
86 ti,bit-shift = <4>;
118 ti,bit-shift = <7>;
134 ti,bit-shift = <6>;
[all …]
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| A D | dra7xx-clocks.dtsi | 255 ti,bit-shift = <23>;
329 ti,bit-shift = <23>;
367 ti,bit-shift = <23>;
405 ti,bit-shift = <23>;
454 ti,bit-shift = <23>;
480 ti,bit-shift = <23>;
554 ti,bit-shift = <23>;
753 ti,bit-shift = <4>;
1193 ti,bit-shift = <8>;
1245 ti,bit-shift = <7>;
[all …]
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| A D | omap36xx-am35xx-omap3430es2plus-clocks.dtsi | 47 ti,bit-shift = <1>;
109 ti,bit-shift = <0>;
117 ti,bit-shift = <0>;
125 ti,bit-shift = <1>;
133 ti,bit-shift = <2>;
141 ti,bit-shift = <2>;
164 ti,bit-shift = <0>;
174 ti,bit-shift = <0>;
182 ti,bit-shift = <1>;
190 ti,bit-shift = <0>;
[all …]
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| A D | am43xx-clocks.dtsi | 12 ti,bit-shift = <31>;
20 ti,bit-shift = <29>;
28 ti,bit-shift = <22>;
108 ti,bit-shift = <0>;
116 ti,bit-shift = <1>;
124 ti,bit-shift = <2>;
132 ti,bit-shift = <4>;
140 ti,bit-shift = <5>;
148 ti,bit-shift = <6>;
350 ti,bit-shift = <8>;
[all …]
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| A D | omap36xx-clocks.dtsi | 19 ti,bit-shift = <0x1e>;
29 ti,bit-shift = <0x1b>;
38 ti,bit-shift = <0xc>;
47 ti,bit-shift = <0x1c>;
56 ti,bit-shift = <0x1f>;
66 ti,bit-shift = <18>;
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| A D | omap36xx-omap3430es2plus-clocks.dtsi | 12 ti,bit-shift = <0>;
20 ti,bit-shift = <8>;
44 ti,bit-shift = <4>;
60 ti,bit-shift = <0>;
67 ti,bit-shift = <9>;
147 ti,bit-shift = <3>;
163 ti,bit-shift = <9>;
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| A D | omap3-u-boot.dtsi | 22 reg-shift = <2>;
27 reg-shift = <2>;
32 reg-shift = <2>;
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| /arch/mips/mach-mtmips/ |
| A D | ddr_cal.c | 75 int maxval, int shift, u32 regval) in dqs_find_max() argument
81 dqsval = regval | (fieldval << shift); in dqs_find_max()
90 int minval, int shift, u32 regval) in dqs_find_min() argument
96 dqsval = regval | (fieldval << shift); in dqs_find_min()
110 u32 dqs_dly_tmp, dqs_dly, test_dqs, shift; in ddr_calibrate() local
145 shift = i * 8; in ddr_calibrate()
146 dqs_dly &= ~(0xff << shift); in ddr_calibrate()
149 dqs_dly_tmp = dqs_dly | (0xf << shift); in ddr_calibrate()
151 0xf, 4 + shift, dqs_dly_tmp); in ddr_calibrate()
156 shift, dqs_dly_tmp); in ddr_calibrate()
[all …]
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| /arch/arm/mach-imx/mx7ulp/ |
| A D | scg.c | 57 u32 shift, mask; in scg_sircdiv_get_rate() local
81 val = (reg & mask) >> shift; in scg_sircdiv_get_rate()
95 u32 shift, mask; in scg_fircdiv_get_rate() local
119 val = (reg & mask) >> shift; in scg_fircdiv_get_rate()
133 u32 shift, mask; in scg_soscdiv_get_rate() local
157 val = (reg & mask) >> shift; in scg_soscdiv_get_rate()
171 u32 shift, mask, gate, valid; in scg_apll_pfd_get_rate() local
208 val = (reg & mask) >> shift; in scg_apll_pfd_get_rate()
221 u32 shift, mask, gate, valid; in scg_spll_pfd_get_rate() local
258 val = (reg & mask) >> shift; in scg_spll_pfd_get_rate()
[all …]
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| /arch/arm/mach-kirkwood/ |
| A D | mpp.c | 55 int shift; in kirkwood_mpp_conf() local
68 shift = (num & 7) << 2; in kirkwood_mpp_conf()
71 sel_save = (mpp_ctrl[num / 8] >> shift) & 0xf; in kirkwood_mpp_conf()
76 mpp_ctrl[num / 8] &= ~(0xf << shift); in kirkwood_mpp_conf()
77 mpp_ctrl[num / 8] |= sel << shift; in kirkwood_mpp_conf()
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| /arch/arm/mach-sunxi/ |
| A D | dram_dw_helpers.c | 90 unsigned int shift, cols, rows; in mctl_auto_detect_dram_size() local
107 shift = config->bus_full_width + 1; in mctl_auto_detect_dram_size()
111 if (mctl_check_pattern(1ULL << (cols + shift))) in mctl_auto_detect_dram_size()
130 shift = config->bus_full_width + 4 + config->cols; in mctl_auto_detect_dram_size()
132 if (mctl_check_pattern(1ULL << (rows + shift))) in mctl_auto_detect_dram_size()
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| A D | clock_sun50i_h6.c | 213 int shift; in clock_twi_onoff() local
218 shift = 0; in clock_twi_onoff()
221 shift = port; in clock_twi_onoff()
227 setbits_le32(ptr, value << shift); in clock_twi_onoff()
229 clrbits_le32(ptr, value << shift); in clock_twi_onoff()
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| /arch/mips/mach-mtmips/mt7620/ |
| A D | sysc.c | 62 u32 val, shift; in mt7620_sysc_ioctl() local
100 shift = GE1_MODE_S; in mt7620_sysc_ioctl()
102 shift = GE2_MODE_S; in mt7620_sysc_ioctl()
105 GE_MODE_M << shift, val << shift); in mt7620_sysc_ioctl()
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| /arch/mips/lib/ |
| A D | reloc.c | 47 unsigned int shift = 0; in read_uint() local
52 val |= (new & 0x7f) << shift; in read_uint()
53 shift += 7; in read_uint()
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| /arch/arm/mach-uniphier/debug-uart/ |
| A D | debug-uart.c | 33 unsigned int shift = pin * mux_bits % 32; in sg_set_pinsel() local
40 tmp &= ~(mask << shift); in sg_set_pinsel()
41 tmp |= (mask & muxval) << shift; in sg_set_pinsel()
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| /arch/mips/mach-octeon/include/mach/ |
| A D | cvmx-fpa3.h | 444 unsigned int shift = 0; in cvmx_fpa3_setup_aura_qos() local
467 for (shift = 0; shift < (1 << 6); shift++) { in cvmx_fpa3_setup_aura_qos()
468 if (0 == ((shift_thresh >> shift) & ~0xffull)) in cvmx_fpa3_setup_aura_qos()
473 aura_level.s.pass = pass_thresh >> shift; in cvmx_fpa3_setup_aura_qos()
474 aura_level.s.drop = drop_thresh >> shift; in cvmx_fpa3_setup_aura_qos()
475 aura_level.s.bp = bp_thresh >> shift; in cvmx_fpa3_setup_aura_qos()
476 aura_level.s.shift = shift; in cvmx_fpa3_setup_aura_qos()
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| /arch/mips/dts/ |
| A D | jz4780.dtsi | 72 reg-shift = <2>;
86 reg-shift = <2>;
100 reg-shift = <2>;
114 reg-shift = <2>;
128 reg-shift = <2>;
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| /arch/arm/mach-exynos/ |
| A D | clock.c | 826 shift = 16; in exynos4_get_mmc_clk()
1477 shift = 0; in exynos5_set_spi_clk()
1482 shift = 16; in exynos5_set_spi_clk()
1487 shift = 0; in exynos5_set_spi_clk()
1492 shift = 0; in exynos5_set_spi_clk()
1497 shift = 12; in exynos5_set_spi_clk()
1535 shift = 20; in exynos5420_set_spi_clk()
1541 shift = 24; in exynos5420_set_spi_clk()
1547 shift = 28; in exynos5420_set_spi_clk()
1553 shift = 16; in exynos5420_set_spi_clk()
[all …]
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| /arch/arm/cpu/arm1136/mx31/ |
| A D | generic.c | 105 unsigned long reg, shift, tmp; in mx31_gpio_mux() local
108 shift = (~mode & 0x3) * 8; in mx31_gpio_mux()
111 tmp &= ~(0xff << shift); in mx31_gpio_mux()
112 tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift; in mx31_gpio_mux()
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| /arch/arm/mach-zynqmp/ |
| A D | psu_spl_init.c | 62 unsigned long shift, unsigned long value) in prog_reg() argument
68 rdata = rdata | (value << shift); in prog_reg()
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| /arch/riscv/dts/ |
| A D | k230.dtsi | 107 reg-shift = <2>;
117 reg-shift = <2>;
127 reg-shift = <2>;
137 reg-shift = <2>;
147 reg-shift = <2>;
|