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/arch/arm/mach-uniphier/
A Ddram_init.c40 size = SZ_64M; in uniphier_memconf_decode()
43 size = SZ_128M; in uniphier_memconf_decode()
52 size = SZ_1G; in uniphier_memconf_decode()
60 size *= 2; in uniphier_memconf_decode()
62 dram_map[0].size = size; in uniphier_memconf_decode()
92 size = SZ_1G; in uniphier_memconf_decode()
100 size *= 2; in uniphier_memconf_decode()
102 dram_map[1].size = size; in uniphier_memconf_decode()
132 size *= 2; in uniphier_memconf_decode()
134 dram_map[2].size = size; in uniphier_memconf_decode()
[all …]
A Dboards.c19 .size = 0x10000000,
23 .size = 0x10000000,
35 .size = 0x20000000,
39 .size = 0x20000000,
48 .size = 0x40000000,
52 .size = 0x40000000,
62 .size = 0x10000000,
66 .size = 0x10000000,
77 .size = 0x20000000,
81 .size = 0x20000000,
[all …]
/arch/arm/mach-apple/
A Dboard.c34 .size = SZ_1G,
42 .size = SZ_1G,
50 .size = SZ_512M,
66 .size = SZ_1G,
95 .size = SZ_1G,
103 .size = SZ_1G,
732 size = gd->bd->bi_dram[0].size; in build_mem_map()
735 size = ALIGN(size, SZ_4K); in build_mem_map()
740 mem_map[i - 2].size = size; in build_mem_map()
753 size = ALIGN(size, SZ_4K); in build_mem_map()
[all …]
/arch/arm/mach-renesas/
A Dmemmap-gen3.c18 .size = 0x40000000UL,
25 .size = 0x03F00000UL,
31 .size = 0x78200000UL,
37 .size = 0x40000000UL,
59 u64 start, size; in enable_caches() local
74 size = gd->bd->bi_dram[bank].size; in enable_caches()
77 if (!size) in enable_caches()
100 gen3_mem_map[i].size = size; in enable_caches()
118 size = gd->bd->bi_dram[bank].size; in enable_caches()
121 if (!size) in enable_caches()
[all …]
A Dmemmap-rzg2l.c23 .size = 0x40000000UL,
30 .size = 0x03F00000UL,
36 .size = 0xF8200000UL,
56 u64 start, size; in enable_caches() local
61 rzg2l_mem_map[i].size = 0x40000000ULL; in enable_caches()
71 size = gd->bd->bi_dram[bank].size; in enable_caches()
74 if (!size) in enable_caches()
82 rzg2l_mem_map[i].size = 0x03F00000ULL; in enable_caches()
89 size += 0x00200000ULL; in enable_caches()
94 rzg2l_mem_map[i].size = size; in enable_caches()
[all …]
/arch/arm/mach-mvebu/
A Ddram.c104 u32 size; in mvebu_sdram_size_adjust() local
138 if (size) { in mv_xor_init2()
144 base += size + 1; in mv_xor_init2()
145 size = (size / (64 << 10)) << 16; in mv_xor_init2()
168 u32 size, temp; in dram_ecc_scrubbing() local
185 if (size == 0) in dram_ecc_scrubbing()
188 total = (u64)size; in dram_ecc_scrubbing()
257 u64 size = 0; in dram_init() local
282 gd->ram_size = size; in dram_init()
293 u64 size = 0; in dram_init_banksize() local
[all …]
A Dmbus.c179 u64 end = (u64)base + size; in mvebu_mbus_window_conflicts()
275 size, remap, in mvebu_mbus_alloc_window()
341 w->size = (size | ~DDR_SIZE_MASK) + 1; in mvebu_mbus_default_setup_cpu_target()
421 u32 size; in mvebu_config_mbus_bridge() local
426 size = 0xffffffff - base + 1; in mvebu_config_mbus_bridge()
427 if (!is_power_of_2(size)) { in mvebu_config_mbus_bridge()
429 size = 1 << (ffs(base) + 1); in mvebu_config_mbus_bridge()
430 base = 0xffffffff - size + 1; in mvebu_config_mbus_bridge()
436 val = (size / (64 << 10)) - 1; in mvebu_config_mbus_bridge()
484 u32 base, size; in mvebu_mbus_probe() local
[all …]
/arch/arm/mach-socfpga/
A Dmmu-arm64_s10.c18 .size = 0x00080000UL,
25 .size = 0x0F7F8000UL,
33 .size = 0x60000000UL,
41 .size = 0x3C0000000UL,
57 .size = 0x80000000UL,
64 .size = 0x780000000UL,
87 .size = 0x80000000UL,
94 .size = 0x60000000UL,
102 .size = 0x08E00000UL,
110 .size = 0x00100000UL,
[all …]
/arch/arm/mach-mvebu/alleycat5/
A Dcpu.c36 .size = 0x100000,
43 .size = 0x3ff00000,
49 .size = SZ_8M,
55 .size = SZ_4M,
61 .size = SZ_512K,
67 .size = SZ_512K,
73 .size = SZ_512K,
80 .size = SZ_512K,
86 .size = SZ_1M,
92 .size = SZ_2G,
[all …]
/arch/powerpc/include/asm/
A Dbitops.h245 return size; in find_next_zero_bit()
246 size -= result; in find_next_zero_bit()
251 if (size < 32) in find_next_zero_bit()
255 size -= 32; in find_next_zero_bit()
262 size -= 32; in find_next_zero_bit()
264 if (!size) in find_next_zero_bit()
334 return size; in ext2_find_next_zero_bit()
335 size -= result; in ext2_find_next_zero_bit()
344 size -= 32; in ext2_find_next_zero_bit()
351 size -= 32; in ext2_find_next_zero_bit()
[all …]
/arch/arm/mach-exynos/
A Dmmu-arm64.c16 .size = 0x10000000UL,
23 .size = 0x80000000UL,
39 .size = 0x10000000UL,
47 .size = 0x3E400000UL,
54 .size = 0x40000000UL,
72 .size = 0x10000000UL,
80 .size = 0x3E400000UL,
106 .size = SZ_2M,
114 .size = SZ_256M,
122 .size = SZ_2G,
[all …]
/arch/x86/include/asm/
A Dcoreboot_tables.h132 u32 size; member
154 u32 size; member
162 u32 size; member
170 u32 size; member
189 u32 size; member
197 u32 size; member
228 u32 size; member
243 u32 size; member
251 u32 size; member
280 u32 size; member
[all …]
/arch/microblaze/include/asm/
A Dbitops.h221 return size; in find_next_zero_bit()
222 size -= result; in find_next_zero_bit()
227 if (size < 32) in find_next_zero_bit()
231 size -= 32; in find_next_zero_bit()
238 size -= 32; in find_next_zero_bit()
240 if (!size) in find_next_zero_bit()
310 return size; in ext2_find_next_zero_bit()
326 if(size < 32) in ext2_find_next_zero_bit()
330 size -= 32; in ext2_find_next_zero_bit()
337 size -= 32; in ext2_find_next_zero_bit()
[all …]
/arch/mips/mach-octeon/include/mach/
A Dcvmx-bootmem.h59 u64 size; member
77 u64 size; member
134 void *cvmx_bootmem_alloc(u64 size, u64 alignment);
162 void *cvmx_bootmem_alloc_address(u64 size, u64 address,
178 void *cvmx_bootmem_alloc_range(u64 size, u64 alignment,
193 void *cvmx_bootmem_alloc_named(u64 size, u64 alignment,
244 void *cvmx_bootmem_alloc_named_range(u64 size, u64 min_addr,
269 void *cvmx_bootmem_alloc_named_range_once(u64 size,
289 int cvmx_bootmem_reserve_memory(u64 start_addr, u64 size,
525 void *__cvmx_phys_addr_to_ptr(u64 phys, int size);
[all …]
/arch/x86/lib/
A De820.c51 entries[0].size = ISA_START_ADDRESS; in install_e820_map()
57 entries[2].size = gd->ram_size - ISA_END_ADDRESS; in install_e820_map()
60 entries[3].size = CONFIG_PCIE_ECAM_SIZE; in install_e820_map()
80 entry->size = size; in e820_add()
83 ctx->addr = addr + size; in e820_add()
88 e820_add(ctx, type, ctx->addr, size); in e820_next()
163 u64 start, size, rgn_top; in lmb_arch_add_memory() local
166 size = e820[i].size; in lmb_arch_add_memory()
167 rgn_top = start + size; in lmb_arch_add_memory()
173 size -= rgn_top - ram_top; in lmb_arch_add_memory()
[all …]
/arch/mips/mach-octeon/
A Dcvmx-range.c44 u64 lsize = size; in cvmx_range_init()
83 index = size - 1; in cvmx_range_find_last_available()
103 u64 i = 0, size; in cvmx_range_alloc_ordered() local
112 while (i < size) { in cvmx_range_alloc_ordered()
167 u64 i, size, r_owner; in cvmx_range_reserve() local
171 if (up > size) { in cvmx_range_reserve()
175 (int)size, (int)up); in cvmx_range_reserve()
202 u64 i, cnt, size; in __cvmx_range_is_allocated() local
210 if (base >= size) { in __cvmx_range_is_allocated()
245 u64 i, size; in cvmx_range_free_with_base() local
[all …]
/arch/arm/mach-mvebu/armada3700/
A Dcpu.c95 if (size) { in get_cpu_dec_win()
136 u32 base, tgt, size; in build_mem_map() local
153 mvebu_mem_map[region].size = size; in build_mem_map()
177 u32 base, tgt, size; in a3700_dram_init() local
200 size_t base, size; member
223 size_t size; in a3700_dram_init_banksize() local
227 u32 base, tgt, size; in a3700_dram_init_banksize() local
238 dram_wins[win].size = size; in a3700_dram_init_banksize()
259 gd->bd->bi_dram[bank - 1].size += size; in a3700_dram_init_banksize()
260 last_end += size; in a3700_dram_init_banksize()
[all …]
/arch/riscv/dts/
A Dk1.dtsi9 #size-cells = <2>;
27 #size-cells = <0>;
77 i-cache-size = <32768>;
80 d-cache-size = <32768>;
107 i-cache-size = <32768>;
110 d-cache-size = <32768>;
137 i-cache-size = <32768>;
140 d-cache-size = <32768>;
167 i-cache-size = <32768>;
170 d-cache-size = <32768>;
[all …]
A Dfu540-c000.dtsi10 #size-cells = <2>;
24 #size-cells = <0>;
46 d-tlb-size = <32>;
52 i-tlb-size = <32>;
70 d-tlb-size = <32>;
76 i-tlb-size = <32>;
94 d-tlb-size = <32>;
100 i-tlb-size = <32>;
118 d-tlb-size = <32>;
124 i-tlb-size = <32>;
[all …]
/arch/powerpc/lib/
A Dmisc.c22 ulong size, bootmap_base; in arch_misc_init() local
35 size = min(bootm_size, get_effective_memsize()); in arch_misc_init()
36 size = min(size, (ulong)CFG_SYS_LINUX_LOWMEM_MAX_SIZE); in arch_misc_init()
38 if (size < bootm_size) { in arch_misc_init()
39 phys_addr_t base = bootmap_base + size; in arch_misc_init()
42 size, (unsigned long long)bootm_size); in arch_misc_init()
44 bootm_size - size, LMB_NONE); in arch_misc_init()
/arch/x86/cpu/efi/
A Dpayload.c35 int ret, size; in board_get_usable_ram_top() local
53 end = (struct efi_mem_desc *)((ulong)map + size); in board_get_usable_ram_top()
81 int size, ret; in dram_init() local
90 end = (struct efi_mem_desc *)((ulong)map + size); in dram_init()
105 int ret, size; in dram_init_banksize() local
114 end = (struct efi_mem_desc *)((ulong)map + size); in dram_init_banksize()
182 int size, ret; in install_e820_map() local
246 entries[num_entries].size = desc->num_pages; in install_e820_map()
247 entries[num_entries].size <<= EFI_PAGE_SHIFT; in install_e820_map()
263 int size, ret; in setup_efi_info() local
[all …]
/arch/mips/include/asm/
A Dbitops.h592 if (!size) in find_first_zero_bit()
737 return size; in find_next_zero_bit()
738 size -= result; in find_next_zero_bit()
747 size -= 32; in find_next_zero_bit()
754 size -= 32; in find_next_zero_bit()
756 if (!size) in find_next_zero_bit()
838 return size; in ext2_find_next_zero_bit()
854 if(size < 32) in ext2_find_next_zero_bit()
858 size -= 32; in ext2_find_next_zero_bit()
865 size -= 32; in ext2_find_next_zero_bit()
[all …]
/arch/arm/mach-stm32mp/
A Ddram_init.c21 int optee_get_reserved_memory(u32 *start, u32 *size) in optee_get_reserved_memory() argument
36 *size = fdt_mem_size; in optee_get_reserved_memory()
59 log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); in dram_init()
61 gd->ram_size = ram.size; in dram_init()
68 phys_size_t size; in board_get_usable_ram_top() local
82 size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE); in board_get_usable_ram_top()
84 reg = ALIGN(gd->ram_top - size, MMU_SECTION_SIZE); in board_get_usable_ram_top()
89 reg = ALIGN(optee_start - size, MMU_SECTION_SIZE); in board_get_usable_ram_top()
94 mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); in board_get_usable_ram_top()
96 return reg + size; in board_get_usable_ram_top()
/arch/arm/dts/
A Djuno-r2.dts21 #size-cells = <2>;
38 #size-cells = <0>;
93 i-cache-size = <0xc000>;
94 i-cache-line-size = <64>;
96 d-cache-size = <0x8000>;
97 d-cache-line-size = <64>;
111 i-cache-size = <0xc000>;
114 d-cache-size = <0x8000>;
129 i-cache-size = <0x8000>;
132 d-cache-size = <0x8000>;
[all …]
/arch/arm/mach-mediatek/
A Dtzcfg.c34 phys_addr_t size; member
40 phys_addr_t size; in fix_tz_region() local
45 region[0].addr, region[0].size); in fix_tz_region()
53 size = gd->ram_top - region[0].addr; in fix_tz_region()
56 region[0].addr, region[0].size, size); in fix_tz_region()
58 region[0].size = size; in fix_tz_region()
77 region[0].size = BL31_DEFAULT_SIZE; in board_get_usable_ram_top()
80 region[0].size = res.a2; in board_get_usable_ram_top()
84 region[0].size); in board_get_usable_ram_top()
90 region[used_regions].size = res.a2; in board_get_usable_ram_top()
[all …]

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