1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * NVIDIA Tegra I2C controller
4 *
5 * Copyright 2010-2011 NVIDIA Corporation
6 */
7
8 #ifndef _TEGRA_I2C_H_
9 #define _TEGRA_I2C_H_
10
11 #include <asm/io.h>
12 #include <asm/types.h>
13 #include <asm/arch/tegra.h>
14
15 struct udevice;
16
17 enum {
18 I2C_TIMEOUT_USEC = 10000, /* Wait time for completion */
19 I2C_FIFO_DEPTH = 8, /* I2C fifo depth */
20 };
21
22 enum i2c_transaction_flags {
23 I2C_IS_WRITE = 0x1, /* for I2C write operation */
24 I2C_IS_10_BIT_ADDRESS = 0x2, /* for 10-bit I2C slave address */
25 I2C_USE_REPEATED_START = 0x4, /* for repeat start */
26 I2C_NO_ACK = 0x8, /* for slave that won't generate ACK */
27 I2C_SOFTWARE_CONTROLLER = 0x10, /* for I2C transfer using GPIO */
28 I2C_NO_STOP = 0x20,
29 };
30
31 /* Contians the I2C transaction details */
32 struct i2c_trans_info {
33 /* flags to indicate the transaction details */
34 enum i2c_transaction_flags flags;
35 u32 address; /* I2C slave device address */
36 u32 num_bytes; /* number of bytes to be transferred */
37 /*
38 * Send/receive buffer. For the I2C send operation this buffer should
39 * be filled with the data to be sent to the slave device. For the I2C
40 * receive operation this buffer is filled with the data received from
41 * the slave device.
42 */
43 u8 *buf;
44 int is_10bit_address;
45 };
46
47 struct i2c_control {
48 u32 tx_fifo;
49 u32 rx_fifo;
50 u32 packet_status;
51 u32 fifo_control;
52 u32 fifo_status;
53 u32 int_mask;
54 u32 int_status;
55 };
56
57 struct dvc_ctlr {
58 u32 ctrl1; /* 00: DVC_CTRL_REG1 */
59 u32 ctrl2; /* 04: DVC_CTRL_REG2 */
60 u32 ctrl3; /* 08: DVC_CTRL_REG3 */
61 u32 status; /* 0C: DVC_STATUS_REG */
62 u32 ctrl; /* 10: DVC_I2C_CTRL_REG */
63 u32 addr_data; /* 14: DVC_I2C_ADDR_DATA_REG */
64 u32 reserved_0[2]; /* 18: */
65 u32 req; /* 20: DVC_REQ_REGISTER */
66 u32 addr_data3; /* 24: DVC_I2C_ADDR_DATA_REG_3 */
67 u32 reserved_1[6]; /* 28: */
68 u32 cnfg; /* 40: DVC_I2C_CNFG */
69 u32 cmd_addr0; /* 44: DVC_I2C_CMD_ADDR0 */
70 u32 cmd_addr1; /* 48: DVC_I2C_CMD_ADDR1 */
71 u32 cmd_data1; /* 4C: DVC_I2C_CMD_DATA1 */
72 u32 cmd_data2; /* 50: DVC_I2C_CMD_DATA2 */
73 u32 reserved_2[2]; /* 54: */
74 u32 i2c_status; /* 5C: DVC_I2C_STATUS */
75 struct i2c_control control; /* 60 ~ 78 */
76 };
77
78 struct i2c_ctlr {
79 u32 cnfg; /* 00: I2C_I2C_CNFG */
80 u32 cmd_addr0; /* 04: I2C_I2C_CMD_ADDR0 */
81 u32 cmd_addr1; /* 08: I2C_I2C_CMD_DATA1 */
82 u32 cmd_data1; /* 0C: I2C_I2C_CMD_DATA2 */
83 u32 cmd_data2; /* 10: DVC_I2C_CMD_DATA2 */
84 u32 reserved_0[2]; /* 14: */
85 u32 status; /* 1C: I2C_I2C_STATUS */
86 u32 sl_cnfg; /* 20: I2C_I2C_SL_CNFG */
87 u32 sl_rcvd; /* 24: I2C_I2C_SL_RCVD */
88 u32 sl_status; /* 28: I2C_I2C_SL_STATUS */
89 u32 sl_addr1; /* 2C: I2C_I2C_SL_ADDR1 */
90 u32 sl_addr2; /* 30: I2C_I2C_SL_ADDR2 */
91 u32 reserved_1[2]; /* 34: */
92 u32 sl_delay_count; /* 3C: I2C_I2C_SL_DELAY_COUNT */
93 u32 reserved_2[4]; /* 40: */
94 struct i2c_control control; /* 50 ~ 68 */
95 u32 clk_div; /* 6C: I2C_I2C_CLOCK_DIVISOR */
96 };
97
98 /* bit fields definitions for IO Packet Header 1 format */
99 #define PKT_HDR1_PROTOCOL_SHIFT 4
100 #define PKT_HDR1_PROTOCOL_MASK (0xf << PKT_HDR1_PROTOCOL_SHIFT)
101 #define PKT_HDR1_CTLR_ID_SHIFT 12
102 #define PKT_HDR1_CTLR_ID_MASK (0xf << PKT_HDR1_CTLR_ID_SHIFT)
103 #define PKT_HDR1_PKT_ID_SHIFT 16
104 #define PKT_HDR1_PKT_ID_MASK (0xff << PKT_HDR1_PKT_ID_SHIFT)
105 #define PROTOCOL_TYPE_I2C 1
106
107 /* bit fields definitions for IO Packet Header 2 format */
108 #define PKT_HDR2_PAYLOAD_SIZE_SHIFT 0
109 #define PKT_HDR2_PAYLOAD_SIZE_MASK (0xfff << PKT_HDR2_PAYLOAD_SIZE_SHIFT)
110
111 /* bit fields definitions for IO Packet Header 3 format */
112 #define PKT_HDR3_READ_MODE_SHIFT 19
113 #define PKT_HDR3_READ_MODE_MASK (1 << PKT_HDR3_READ_MODE_SHIFT)
114 #define PKT_HDR3_REPEAT_START_SHIFT 16
115 #define PKT_HDR3_REPEAT_START_MASK (1 << PKT_HDR3_REPEAT_START_SHIFT)
116 #define PKT_HDR3_SLAVE_ADDR_SHIFT 0
117 #define PKT_HDR3_SLAVE_ADDR_MASK (0x3ff << PKT_HDR3_SLAVE_ADDR_SHIFT)
118
119 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT 26
120 #define DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK \
121 (1 << DVC_CTRL_REG3_I2C_HW_SW_PROG_SHIFT)
122
123 /* I2C_CNFG */
124 #define I2C_CNFG_NEW_MASTER_FSM_SHIFT 11
125 #define I2C_CNFG_NEW_MASTER_FSM_MASK (1 << I2C_CNFG_NEW_MASTER_FSM_SHIFT)
126 #define I2C_CNFG_PACKET_MODE_SHIFT 10
127 #define I2C_CNFG_PACKET_MODE_MASK (1 << I2C_CNFG_PACKET_MODE_SHIFT)
128
129 /* I2C_SL_CNFG */
130 #define I2C_SL_CNFG_NEWSL_SHIFT 2
131 #define I2C_SL_CNFG_NEWSL_MASK (1 << I2C_SL_CNFG_NEWSL_SHIFT)
132
133 /* I2C_FIFO_STATUS */
134 #define TX_FIFO_FULL_CNT_SHIFT 0
135 #define TX_FIFO_FULL_CNT_MASK (0xf << TX_FIFO_FULL_CNT_SHIFT)
136 #define TX_FIFO_EMPTY_CNT_SHIFT 4
137 #define TX_FIFO_EMPTY_CNT_MASK (0xf << TX_FIFO_EMPTY_CNT_SHIFT)
138
139 /* I2C_INTERRUPT_STATUS */
140 #define I2C_INT_XFER_COMPLETE_SHIFT 7
141 #define I2C_INT_XFER_COMPLETE_MASK (1 << I2C_INT_XFER_COMPLETE_SHIFT)
142 #define I2C_INT_NO_ACK_SHIFT 3
143 #define I2C_INT_NO_ACK_MASK (1 << I2C_INT_NO_ACK_SHIFT)
144 #define I2C_INT_ARBITRATION_LOST_SHIFT 2
145 #define I2C_INT_ARBITRATION_LOST_MASK (1 << I2C_INT_ARBITRATION_LOST_SHIFT)
146
147 /* I2C_CLK_DIVISOR_REGISTER */
148 #define CLK_DIV_STD_FAST_MODE 0x19
149 #define CLK_DIV_HS_MODE 1
150 #define CLK_MULT_STD_FAST_MODE 8
151
152 /**
153 * Returns the bus number of the DVC controller
154 *
155 * Return: number of bus, or -1 if there is no DVC active
156 */
157 int tegra_i2c_get_dvc_bus(struct udevice **busp);
158
159 /* Pre-dm section used for initial setup of PMIC */
160 #define I2C_SEND_2_BYTES 0x0A02
161
tegra_i2c_ll_write(uint addr,uint data)162 static inline void tegra_i2c_ll_write(uint addr, uint data)
163 {
164 struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
165
166 writel(addr, ®->cmd_addr0);
167 writel(0x2, ®->cnfg);
168
169 writel(data, ®->cmd_data1);
170 writel(I2C_SEND_2_BYTES, ®->cnfg);
171 }
172
173 void pmic_enable_cpu_vdd(void);
174
175 #endif /* _TEGRA_I2C_H_ */
176