Home
last modified time | relevance | path

Searched refs:src_top2 (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init_exynos5.c567 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK); in exynos5250_system_clock_init()
568 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK); in exynos5250_system_clock_init()
569 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK); in exynos5250_system_clock_init()
570 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK); in exynos5250_system_clock_init()
691 writel(TOP2_VAL, &clk->src_top2); in exynos5250_system_clock_init()
735 val = readl(&clk->src_top2); in exynos5250_system_clock_init()
737 writel(val, &clk->src_top2); in exynos5250_system_clock_init()
915 writel(CLK_SRC_TOP2_VAL, &clk->src_top2); in exynos5420_system_clock_init()
A Dclock.c1343 setbits_le32(&clk->src_top2, CLK_SRC_MOUT_EPLL); in exynos5_set_i2s_clk_source()
/arch/arm/mach-exynos/include/mach/
A Dclock.h677 unsigned int src_top2; member
1073 unsigned int src_top2; member

Completed in 18 milliseconds