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/arch/mips/mach-ath79/qca953x/
A Dlowlevel_init.S81 #define MK_PLL_DDR_DIT_FRAC(max, min, step, cnt) \ argument
85 PLL_DDR_DIT_FRAC_STEP(step) | \
87 #define MK_PLL_CPU_DIT_FRAC(max, min, step, cnt) \ argument
91 PLL_CPU_DIT_FRAC_STEP(step) | \
/arch/arm/dts/
A Darmada-xp-db-xc3-24g4xg-u-boot.dtsi11 nand-ecc-step-size = <512>;
A Dam335x-pocketbeagle.dts189 ti,chan-step-avg = <16 16 16 16 16 16 16 16>;
190 ti,chan-step-opendelay = <0x98 0x98 0x98 0x98 0x98 0x98 0x98 0x98>;
191 ti,chan-step-sampledelay = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
A Dns-board.dts45 nand-ecc-step-size = <512>;
A Dimx6q.dtsi47 clock-names = "arm", "pll2_pfd2_396m", "step",
84 clock-names = "arm", "pll2_pfd2_396m", "step",
119 clock-names = "arm", "pll2_pfd2_396m", "step",
154 clock-names = "arm", "pll2_pfd2_396m", "step",
A Dsun8i-r16-nintendo-nes-classic.dts41 nand-ecc-step-size = <1024>;
A Dbcm96753ref.dts74 nand-ecc-step-size = <512>;
A Dbcm968580xref.dts72 nand-ecc-step-size = <512>;
A Dbcm968360bg.dts72 nand-ecc-step-size = <512>;
A Dimx6dl.dtsi42 clock-names = "arm", "pll2_pfd2_396m", "step",
75 clock-names = "arm", "pll2_pfd2_396m", "step",
A Dzynqmp-zc1751-xm017-dc3.dts142 nand-ecc-step-size = <1024>;
178 nand-ecc-step-size = <1024>;
A Dimx8ulp.dtsi367 fsl,tuning-step = <2>;
382 fsl,tuning-step = <2>;
397 fsl,tuning-step = <2>;
A Dimx8qm-cgtqmx8.dts390 fsl,tuning-step= <2>;
403 fsl,tuning-step= <2>;
A Dimx7-cm.dts238 tuning-step = <2>;
256 fsl,tuning-step = <2>;
A Dca-presidio-engboard.dts65 nand-ecc-step-size = <1024>; /* Must be 1024 */
A Dac5-98dx35xx-atl-x240.dts50 nand-ecc-step-size = <512>;
A Dimxrt1020.dtsi90 fsl,tuning-step= <2>;
/arch/arm/mach-nexell/
A Dclock.c228 static inline void clk_dev_rate(void *base, int step, int src, int div) in clk_dev_rate() argument
233 val = readl(&reg->con_gen[step << 1]); in clk_dev_rate()
238 writel(val, &reg->con_gen[step << 1]); in clk_dev_rate()
241 static inline void clk_dev_inv(void *base, int step, int inv) in clk_dev_inv() argument
244 unsigned int val = readl(&reg->con_gen[step << 1]) & ~(1 << 1); in clk_dev_inv()
247 writel(val, &reg->con_gen[step << 1]); in clk_dev_inv()
614 int step, div[2] = { 0, }; in clk_round_rate() local
622 step = peri->clk_step; in clk_round_rate()
656 for (i = 0; step > i ; i++) in clk_round_rate()
681 step = 1; in clk_round_rate()
/arch/mips/dts/
A Dbrcm,bcm968380gerg.dts61 nand-ecc-step-size = <512>;
A Dci20.dts69 nand-ecc-step-size = <1024>;
A Dcomtrend,vr-3032u.dts109 nand-ecc-step-size = <512>;
/arch/arm/mach-imx/mx6/
A Dsoc.c265 u32 val, step, old, reg = readl(&anatop->reg_core); in set_ldo_voltage() local
296 step = abs(val - old); in set_ldo_voltage()
297 if (step == 0) in set_ldo_voltage()
307 udelay(3 * step); in set_ldo_voltage()
/arch/arm/mach-omap2/omap5/
A Dhw_data.c280 .step = 10000, /* 10 mV represented in uV */
295 .step = 10000, /* 10 mV represented in uV */
310 .step = 5000, /* 5 mV represented in uV */
326 .step = 5000, /* 5 mV represented in uV */
/arch/sandbox/dts/
A Dsandbox_pmic.dtsi62 * VAL2REG(min, step, value) [uV/uA]
/arch/arm/mach-uniphier/dram/
A Dumc-pxs2.c95 static void ddrphy_dqs_delay_fixup(void __iomem *phy_base, int nr_dx, int step) in ddrphy_dqs_delay_fixup() argument
106 rdqsd = clamp(rdqsd + step, 0U, 0xffU); in ddrphy_dqs_delay_fixup()

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