| /arch/mips/mach-mtmips/mt7620/ |
| A D | init.c | 41 setbits_32(sysc + SYSCTL_CPLL_CFG0_REG, CPLL_SW_CFG); in cpu_pll_init()
44 setbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); in cpu_pll_init()
52 clrbits_32(sysc + SYSCTL_CPLL_CFG1_REG, CPLL_PD); in cpu_pll_init()
62 clrsetbits_32(sysc + SYSCTL_CPU_SYS_CLKCFG_REG, in cpu_pll_init()
92 val = readl(sysc + SYSCTL_SYSCFG0_REG); in mt7620_get_clks()
101 val = readl(sysc + SYSCTL_CPLL_CFG1_REG); in mt7620_get_clks()
107 val = readl(sysc + SYSCTL_CPLL_CFG0_REG); in mt7620_get_clks()
118 val = readl(sysc + SYSCTL_CUR_CLK_STS_REG); in mt7620_get_clks()
153 val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); in print_cpuinfo()
158 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()
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| A D | dram.c | 59 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in mt7620_memc_reset() local
62 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7620_memc_reset()
64 clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7620_memc_reset()
69 void __iomem *sysc; in mt7620_dram_init() local
74 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in mt7620_dram_init()
75 ddr_type = (readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE_M) in mt7620_dram_init()
77 aux = readl(sysc + SYSCTL_CPLL_CFG1_REG) & in mt7620_dram_init()
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| A D | Makefile | 9 obj-y += sysc.o
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| /arch/arm/dts/ |
| A D | am33xx-l4.dtsi | 34 compatible = "ti,sysc-omap4", "ti,sysc";
90 compatible = "ti,sysc-omap4", "ti,sysc";
131 compatible = "ti,sysc-omap2", "ti,sysc";
176 compatible = "ti,sysc-omap2", "ti,sysc";
207 compatible = "ti,sysc-omap2", "ti,sysc";
230 compatible = "ti,sysc-omap4", "ti,sysc";
266 compatible = "ti,sysc-omap4", "ti,sysc";
369 compatible = "ti,sysc-omap2", "ti,sysc";
700 compatible = "ti,sysc-pruss", "ti,sysc";
868 compatible = "ti,sysc-omap2", "ti,sysc";
[all …]
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| A D | omap36xx.dtsi | 8 #include <dt-bindings/bus/ti-sysc.h>
96 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
99 reg-names = "sysc";
100 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
101 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
118 compatible = "ti,sysc-omap3630-sr", "ti,sysc";
121 reg-names = "sysc";
122 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>;
123 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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| A D | am33xx.dtsi | 8 #include <dt-bindings/bus/ti-sysc.h>
209 compatible = "ti,sysc-omap4", "ti,sysc";
236 compatible = "ti,sysc-omap4", "ti,sysc";
239 reg-names = "rev", "sysc";
259 compatible = "ti,sysc-omap4", "ti,sysc";
262 reg-names = "rev", "sysc";
282 compatible = "ti,sysc-omap4", "ti,sysc";
305 compatible = "ti,sysc-omap2", "ti,sysc";
624 compatible = "ti,sysc-omap3-sham", "ti,sysc";
652 compatible = "ti,sysc-omap2", "ti,sysc";
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| A D | r8a779g0-u-boot.dtsi | 105 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
112 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
120 power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
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| A D | r8a779f0-u-boot.dtsi | 15 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
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| /arch/mips/mach-mtmips/mt7628/ |
| A D | init.c | 20 void __iomem *sysc; in set_init_timer_freq() local
23 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in set_init_timer_freq()
26 bs = readl(sysc + SYSCTL_SYSCFG0_REG); in set_init_timer_freq()
35 val = readl(sysc + SYSCTL_CLKCFG0_REG); in set_init_timer_freq()
49 void __iomem *sysc; in print_cpuinfo() local
56 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in print_cpuinfo()
58 val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); in print_cpuinfo()
63 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()
67 val = readl(sysc + SYSCTL_EFUSE_CFG_REG); in print_cpuinfo()
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| A D | ddr.c | 66 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in mt7628_memc_reset() local
69 setbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
71 clrbits_32(sysc + SYSCTL_RSTCTL_REG, MC_RST); in mt7628_memc_reset()
132 void __iomem *sysc; in mt7628_ddr_init() local
136 sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in mt7628_ddr_init()
137 ddr_type = readl(sysc + SYSCTL_SYSCFG0_REG) & DRAM_TYPE; in mt7628_ddr_init()
138 pkg_type = !!(readl(sysc + SYSCTL_CHIP_REV_ID_REG) & PKG_ID); in mt7628_ddr_init()
139 lspd = readl(sysc + SYSCTL_CLKCFG0_REG) & in mt7628_ddr_init()
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| /arch/mips/mach-mtmips/mt7621/ |
| A D | init.c | 30 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in print_cpuinfo() local
38 val = readl(sysc + SYSCTL_CHIP_REV_ID_REG); in print_cpuinfo()
44 val = readl(sysc + SYSCTL_SYSCFG0_REG); in print_cpuinfo()
89 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in get_xtal_mhz() local
92 bs = readl(sysc + SYSCTL_SYSCFG0_REG); in get_xtal_mhz()
242 void __iomem *sysc = ioremap_nocache(SYSCTL_BASE, SYSCTL_SIZE); in _machine_restart() local
245 writel(SYS_RST, sysc + SYSCTL_RSTCTL_REG); in _machine_restart()
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| /arch/mips/dts/ |
| A D | mt7620.dtsi | 29 sysc: sysc@10000000 { label
30 compatible = "mediatek,mt7620-sysc";
36 mediatek,sysc = <&sysc>;
243 mediatek,sysc = <&sysc>;
263 mediatek,sysc = <&sysc>;
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| A D | mt7628a.dtsi | 44 sysc: system-controller@0 { label
45 compatible = "ralink,mt7620a-sysc", "syscon";
370 syscon = <&sysc>;
379 ralink,sysctl = <&sysc>;
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| A D | mt7621.dtsi | 50 sysc: sysctrl@1e000000 { label
51 compatible = "mediatek,mt7621-sysc", "syscon";
247 mediatek,ethsys = <&sysc>;
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| A D | mt7621-u-boot.dtsi | 16 &sysc {
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| /arch/mips/mach-mtmips/mt7621/spl/ |
| A D | launch.c | 58 void __iomem *sysc = (void __iomem *)KSEG1ADDR(SYSCTL_BASE); in secondary_cpu_init() local
66 dual_core = readl(sysc + SYSCTL_CHIP_REV_ID_REG) & CPU_ID; in secondary_cpu_init()
73 writel((uintptr_t)_start, sysc + BOOT_SRAM_BASE_REG); in secondary_cpu_init()
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| /arch/arm/include/asm/ |
| A D | ehci-omap.h | 78 u32 sysc; /* 0x10 */ member
92 u32 sysc; /* 0x10 */ member
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