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/arch/arm/cpu/armv8/fsl-layerscape/
A Dmp.c35 u64 *table = get_spin_tbl_addr(); in update_os_arch_secondary_cores() local
40 table[i * WORDS_PER_SPIN_TABLE_ENTRY + in update_os_arch_secondary_cores()
43 table[i * WORDS_PER_SPIN_TABLE_ENTRY + in update_os_arch_secondary_cores()
86 u64 *table; in fsl_layerscape_wake_seconday_cores() local
133 table = get_spin_tbl_addr(); in fsl_layerscape_wake_seconday_cores()
136 (unsigned long)table + in fsl_layerscape_wake_seconday_cores()
197 flush_dcache_range((unsigned long)table, (unsigned long)table + in fsl_layerscape_wake_seconday_cores()
230 u64 *table = get_spin_tbl_addr(); in is_core_online() local
278 u64 *table = get_spin_tbl_addr(); in cpu_status() local
288 printf("table @ 0x%p\n", table); in cpu_status()
[all …]
/arch/x86/lib/
A Dsfi.c27 u64 table[SFI_TABLE_MAX_ENTRIES]; member
68 *entry++ = tab->table[i]; in sfi_write_system_header()
134 struct table_info table; in write_sfi_table() local
136 table.base = base; in write_sfi_table()
137 table.ptr = 0; in write_sfi_table()
138 table.count = 0; in write_sfi_table()
139 sfi_write_cpus(&table); in write_sfi_table()
140 sfi_write_apic(&table); in write_sfi_table()
146 sfi_write_xsdt(&table); in write_sfi_table()
149 sfi_write_system_header(&table); in write_sfi_table()
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A Dtables.c108 const struct table_info *table = &table_list[i]; in write_tables() local
109 int size = table->size ? : CONFIG_ROM_TABLE_SIZE; in write_tables()
114 if (!strcmp("smbios", table->name)) in write_tables()
117 if (IS_ENABLED(CONFIG_BLOBLIST_TABLES) && table->tag) { in write_tables()
120 rom_addr = (ulong)bloblist_add(table->tag, size, in write_tables()
121 ilog2(table->align)); in write_tables()
129 if (table->tag == BLOBLISTT_SMBIOS_TABLES) in write_tables()
132 rom_table_end = table->write(rom_addr); in write_tables()
142 if (!table->write(high_table)) { in write_tables()
157 debug("- wrote '%s' to %x, end %x\n", table->name, in write_tables()
A Dasm-offsets.c23 DEFINE(GD_TABLE, offsetof(gd_t, arch.table)); in main()
A Dbdinfo.c19 bdinfo_print_num_l("prev table", gd->arch.table); in arch_print_bdinfo()
/arch/arm/mach-socfpga/
A Dwrap_iocsr_config.c14 const unsigned long **table, in iocsr_get_config_table() argument
19 *table = iocsr_scan_chain0_table; in iocsr_get_config_table()
23 *table = iocsr_scan_chain1_table; in iocsr_get_config_table()
27 *table = iocsr_scan_chain2_table; in iocsr_get_config_table()
31 *table = iocsr_scan_chain3_table; in iocsr_get_config_table()
A Dwrap_pinmux_config.c13 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len) in sysmgr_get_pinmux_table() argument
15 *table = sys_mgr_init_table; in sysmgr_get_pinmux_table()
A Dwrap_handoff_soc64.c95 int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len) in socfpga_handoff_read() argument
98 u32 *table_x32 = table; in socfpga_handoff_read()
/arch/arm/include/asm/armv8/
A Dmmu.h113 static inline void set_ttbr_tcr_mair(int el, u64 table, u64 tcr, u64 attr) in set_ttbr_tcr_mair() argument
117 asm volatile("msr ttbr0_el1, %0" : : "r" (table) : "memory"); in set_ttbr_tcr_mair()
121 asm volatile("msr ttbr0_el2, %0" : : "r" (table) : "memory"); in set_ttbr_tcr_mair()
125 asm volatile("msr ttbr0_el3, %0" : : "r" (table) : "memory"); in set_ttbr_tcr_mair()
134 static inline void get_ttbr_tcr_mair(int el, u64 *table, u64 *tcr, u64 *attr) in get_ttbr_tcr_mair() argument
137 asm volatile("mrs %0, ttbr0_el1" : "=r" (*table)); in get_ttbr_tcr_mair()
141 asm volatile("mrs %0, ttbr0_el2" : "=r" (*table)); in get_ttbr_tcr_mair()
145 asm volatile("mrs %0, ttbr0_el3" : "=r" (*table)); in get_ttbr_tcr_mair()
/arch/powerpc/cpu/mpc85xx/
A Dmp.c64 u32 *table, id = get_my_id(); in cpu_status() local
70 table = (u32 *)&__spin_table; in cpu_status()
71 printf("table base @ 0x%p\n", table); in cpu_status()
75 table = (u32 *)&__spin_table + nr * NUM_BOOT_ENTRY; in cpu_status()
78 printf("table @ 0x%p\n", table); in cpu_status()
80 printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3_LOWER]); in cpu_status()
81 printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); in cpu_status()
171 table[entry] = val; in cpu_release()
175 table[BOOT_ENTRY_ADDR_UPPER] = (u32)(boot_addr >> 32); in cpu_release()
257 u32 *table = (u32 *)&__spin_table; in plat_mp_up() local
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/arch/x86/cpu/efi/
A Dpayload.c152 debug("table=%lx\n", gd->arch.table); in reserve_arch()
153 if (!gd->arch.table) in reserve_arch()
156 hdr = (struct efi_info_hdr *)gd->arch.table; in reserve_arch()
161 gd->arch.table, gd->start_addr_sp, hdr->total_size); in reserve_arch()
162 gd->arch.table = gd->start_addr_sp; in reserve_arch()
260 struct efi_entry_systable *table; in setup_efi_info() local
272 efi_info->efi_systab = (u32)(table->sys_table); in setup_efi_info()
285 efi_info->efi_systab_hi = table->sys_table >> 32; in setup_efi_info()
296 struct efi_entry_systable *table = NULL; in efi_show_bdinfo() local
302 bdinfo_print_num_l("efi_table", table->sys_table); in efi_show_bdinfo()
[all …]
/arch/arm/dts/
A Dbcm2837.dtsi47 enable-method = "spin-table";
55 enable-method = "spin-table";
63 enable-method = "spin-table";
71 enable-method = "spin-table";
A Dsun8i-r40-cpu-opp.dtsi2 cpu0_opp_table: opp-table-cpu {
A Drk3229.dtsi13 cpu0_opp_table: opp-table-0 {
/arch/arm/mach-tegra/tegra20/
A Demc.c244 const u32 *table = NULL; in tegra_set_emc() local
247 err = decode_emc(blob, rate, &emc, &table); in tegra_set_emc()
256 u32 value = fdt32_to_cpu(table[i]); in tegra_set_emc()
/arch/arm/cpu/armv8/
A Dcache_v8.c264 static void set_pte_table(u64 *pte, u64 *table) in set_pte_table() argument
267 debug("Setting %p to addr=%p\n", pte, table); in set_pte_table()
268 *pte = PTE_TYPE_TABLE | (ulong)table; in set_pte_table()
303 u64 *table, u64 attrs) in map_range() argument
315 table[i] = phys | attrs | PTE_TYPE_PAGE; in map_range()
317 table[i] = phys | attrs; in map_range()
327 if (pte_type(&table[i]) == PTE_TYPE_FAULT) in map_range()
328 set_pte_table(&table[i], create_table()); in map_range()
330 split_block(&table[i], level); in map_range()
466 u64 *table = (u64 *)addr; in __pagetable_walk() local
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/arch/arm/mach-versal/
A DKconfig32 MMU table than the one which will be allocated during
40 memory attributes in MMU table entry.
/arch/nios2/cpu/
A Du-boot.lds30 * the initialization code relocates the command table as
100 /* DEBUG -- symbol table, string table, etc. etc.
/arch/arm/mach-socfpga/include/mach/
A Dscan_manager.h22 const unsigned long **table,
A Dsystem_manager_gen5.h14 void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
/arch/powerpc/cpu/mpc8xxx/
A Dfsl_lbc.c110 void upmconfig(uint upm, uint *table, uint size) in upmconfig() argument
143 out_be32(&lbc->mdr, table[i]); in upmconfig()
/arch/mips/cpu/
A Du-boot.lds47 * Space for relocation table
51 * section to abort relocation if the table
/arch/x86/
A DKconfig729 those tables, including PIRQ routing table, Multi-Processor
730 table and ACPI table.
762 bool "Generate a PIRQ table"
764 Generate a PIRQ routing table for this board. The PIRQ routing table
771 bool "Generate a SFI (Simple Firmware Interface) table"
785 bool "Generate an MP (Multi-Processor) table"
787 Generate an MP (Multi-Processor) table for this board. The MP table
1021 bool "Support ACPI table generation for Intel SoCs"
1027 to create a GNVS table and set it up.
1030 bool "Generate ACPI table for Intel GMA graphics"
[all …]
/arch/powerpc/cpu/mpc8xx/
A Dcpu.c183 void upmconfig(uint upm, uint *table, uint size) in upmconfig() argument
191 out_be32(&memctl->memc_mdr, table[i]); /* (16-15) */ in upmconfig()
/arch/arm/mach-imx/imx9/
A Dsoc.c648 struct low_drive_freq_entry table[] = { in low_drive_freq_update() local
654 for (i = 0; i < ARRAY_SIZE(table); i++) { in low_drive_freq_update()
655 nodeoff = fdt_path_offset(blob, table[i].node_path); in low_drive_freq_update()
657 ret = low_drive_fdt_fix_clock(blob, nodeoff, table[i].clk, in low_drive_freq_update()
658 table[i].new_rate); in low_drive_freq_update()
660 printf("freq update failed for %s\n", table[i].node_path); in low_drive_freq_update()

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