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Searched refs:timing_ref (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h83 unsigned timing_ref; member
A Ddmc_init_ddr3.c126 writel(mem->timing_ref, &dmc->timingref); in ddr3_mem_ctrl_init()
606 writel(mem->timing_ref, &drex0->timingref); in ddr3_mem_ctrl_init()
607 writel(mem->timing_ref, &drex1->timingref); in ddr3_mem_ctrl_init()
A Dclock_init_exynos5.c187 .timing_ref = 0x000000bb,
290 .timing_ref = 0x000000bb,
393 .timing_ref = 0x000000bb,

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