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Searched refs:timing_row (Results 1 – 3 of 3) sorted by relevance

/arch/arm/mach-exynos/
A Dclock_init.h84 unsigned timing_row; member
A Ddmc_init_ddr3.c127 writel(mem->timing_row, &dmc->timingrow); in ddr3_mem_ctrl_init()
608 writel(mem->timing_row, &drex0->timingrow0); in ddr3_mem_ctrl_init()
609 writel(mem->timing_row, &drex1->timingrow0); in ddr3_mem_ctrl_init()
A Dclock_init_exynos5.c188 .timing_row = 0x6836650f,
291 .timing_row = 0x8c36650e,
394 .timing_row = 0x8c36650e,

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