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Searched refs:timingdata0 (Results 1 – 2 of 2) sorted by relevance

/arch/arm/mach-exynos/include/mach/
A Ddmc.h222 unsigned int timingdata0; member
/arch/arm/mach-exynos/
A Ddmc_init_ddr3.c610 writel(mem->timing_data, &drex0->timingdata0); in ddr3_mem_ctrl_init()
611 writel(mem->timing_data, &drex1->timingdata0); in ddr3_mem_ctrl_init()

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