Home
last modified time | relevance | path

Searched refs:timings (Results 1 – 25 of 76) sorted by relevance

1234

/arch/arm/mach-imx/
A Dddrmc-vf610.c125 writel(DDRMC_CR12_WRLAT(timings->wrlat) | in ddrmc_ctrl_init_ddr3()
127 writel(DDRMC_CR13_TRC(timings->trc) | DDRMC_CR13_TRRD(timings->trrd) | in ddrmc_ctrl_init_ddr3()
128 DDRMC_CR13_TCCD(timings->tccd) | in ddrmc_ctrl_init_ddr3()
131 writel(DDRMC_CR14_TFAW(timings->tfaw) | DDRMC_CR14_TRP(timings->trp) | in ddrmc_ctrl_init_ddr3()
132 DDRMC_CR14_TWTR(timings->twtr) | in ddrmc_ctrl_init_ddr3()
134 writel(DDRMC_CR16_TMRD(timings->tmrd) | in ddrmc_ctrl_init_ddr3()
152 writel(DDRMC_CR26_TREF(timings->tref) | in ddrmc_ctrl_init_ddr3()
158 writel(DDRMC_CR31_TXSNR(timings->txsnr) | in ddrmc_ctrl_init_ddr3()
161 writel(DDRMC_CR34_CKSRX(timings->cksrx) | in ddrmc_ctrl_init_ddr3()
172 writel(DDRMC_CR66_ZQCL(timings->zqcl) | in ddrmc_ctrl_init_ddr3()
[all …]
/arch/arm/mach-omap2/omap3/
A Dsdrc.c102 struct board_sdrc_timings *timings) in write_sdrc_timings() argument
105 writel(timings->mcfg, &sdrc_base->cs[cs].mcfg); in write_sdrc_timings()
106 writel(timings->ctrla, &sdrc_actim_base->ctrla); in write_sdrc_timings()
107 writel(timings->ctrlb, &sdrc_actim_base->ctrlb); in write_sdrc_timings()
113 writel(timings->mr, &sdrc_base->cs[cs].mr); in write_sdrc_timings()
132 struct board_sdrc_timings timings; in do_sdrc_init() local
138 timings.sharing = SDRC_SHARING; in do_sdrc_init()
151 get_board_mem_timings(&timings); in do_sdrc_init()
161 writel(timings.sharing, &sdrc_base->sharing); in do_sdrc_init()
184 timings.mcfg = readl(&sdrc_base->cs[CS0].mcfg), in do_sdrc_init()
[all …]
/arch/arm/mach-omap2/
A Demif-common.c619 const struct lpddr2_ac_timings *timings = 0; in get_timings_table() local
637 timings = device_timings[i]; in get_timings_table()
641 return timings; in get_timings_table()
712 val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1; in get_sdram_tim_1_reg()
734 val = max(min_tck->tCKE, timings->tCKE) - 1; in get_sdram_tim_2_reg()
744 val = ns_2_cycles(timings->tXSR) - 1; in get_sdram_tim_2_reg()
762 val = ns_2_cycles(timings->tRFCab) - 1; in get_sdram_tim_3_reg()
765 val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1; in get_sdram_tim_3_reg()
768 val = ns_2_cycles(timings->tZQCS) - 1; in get_sdram_tim_3_reg()
926 const struct lpddr2_ac_timings *timings; in emif_calculate_regs() local
[all …]
A DKconfig147 the timings to use or use pre-determined timings (based on using the
/arch/arm/dts/
A Dimx6ul-14x14-evk-u-boot.dtsi31 display-timings {
A Dimx6ul-opos6uldev-u-boot.dtsi26 display-timings {
A Dimx7d-colibri-eval-v3-u-boot.dtsi33 display-timings {
A Dimx7d-colibri-emmc-eval-v3-u-boot.dtsi33 display-timings {
A Dimx6q-icore.dts42 display-timings {
A Dimx6ull-colibri-emmc-eval-v3-u-boot.dtsi45 display-timings {
A Dimx6ull-colibri-eval-v3-u-boot.dtsi45 display-timings {
A Dtegra20-medcom-wide.dts66 nvidia,panel-timings = <0 0 0 0>;
A Dtegra20-tec.dts78 nvidia,panel-timings = <0 0 0 0>;
A Dat91sam9x5dm.dtsi33 display-timings {
A Dsama5d3xdm.dtsi22 display-timings {
A Dam335x-pxm50.dts41 display-timings {
A Dimx7d-pico-pi-u-boot.dtsi33 display-timings {
A Domap-gpmc-smsc9221.dtsi6 * or smsc 9218) has faster timings, leading to higher
A Dimx6dl-brppt2.dts77 display-timings {
183 display-timings {
/arch/x86/cpu/quark/
A Ddram.c41 memcpy(&mrc_params->timings, cache->data, cache->data_size); in prepare_mrc_cache()
161 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); in dram_init()
/arch/arm/mach-at91/include/mach/
A Dsama5d2_smc.h23 u32 timings; /* 0x60C SMC Cycle Register */ member
A Dsama5d3_smc.h23 u32 timings; /* 0x60C SMC Cycle Register */ member
/arch/arm/include/asm/arch-omap3/
A Dsys_proto.h38 void get_board_mem_timings(struct board_sdrc_timings *timings);
/arch/arm/include/asm/arch-vf610/
A Dddrmc-vf610.h78 void ddrmc_ctrl_init_ddr3(struct ddr3_jedec_timings const *timings,
/arch/x86/include/asm/arch-quark/
A Dmrc.h156 struct mrc_timings timings; member

Completed in 37 milliseconds

1234