Searched refs:total (Results 1 – 17 of 17) sorted by relevance
| /arch/arm/mach-imx/ |
| A D | spl_imx_romapi.c | 172 ulong total = sector + count; in spl_ram_load_read() local
174 if (total > *p) in spl_ram_load_read()
175 *p = total; in spl_ram_load_read()
243 int total = get_container_size((ulong)img_hdr, NULL); in img_total_size() local
245 if (total < 0) { in img_total_size()
250 return total; in img_total_size()
266 int total; in spl_romapi_load_image_stream() local
342 total = img_total_size(phdr); in spl_romapi_load_image_stream()
343 total += 3; in spl_romapi_load_image_stream()
344 total &= ~0x3; in spl_romapi_load_image_stream()
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| /arch/x86/cpu/tangier/ |
| A D | sdram.c | 109 int type, total = 0; in sfi_setup_e820() local
136 if (total == E820MAX) in sfi_setup_e820()
138 entries[total].addr = start; in sfi_setup_e820()
139 entries[total].size = size; in sfi_setup_e820()
140 entries[total].type = type; in sfi_setup_e820()
142 total++; in sfi_setup_e820()
145 return total; in sfi_setup_e820()
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| A D | Kconfig | 30 Note this size must not exceed eSRAM's total size.
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| /arch/x86/cpu/qemu/ |
| A D | dram.c | 50 u64 total = gd->ram_size; in dram_init() local
53 if (total > SZ_2G + SZ_1G) in dram_init()
54 total += SZ_1G; in dram_init()
55 ret = mtrr_add_request(MTRR_TYPE_WRBACK, 0, total); in dram_init()
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| /arch/arm/mach-mvebu/ |
| A D | dram.c | 170 u64 total; in dram_ecc_scrubbing() local
188 total = (u64)size; in dram_ecc_scrubbing()
189 total_mem += (u32)(total / (1 << 30)); in dram_ecc_scrubbing()
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| /arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| A D | README.qspi | 25 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
36 SF: Detected S25FL256S_64K with page size 256 Bytes, erase size 64 KiB, total 32 MiB
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| A D | README.lsch3 | 16 - Region 2 is at 0x80_8000_0000 to the top of total memory,
22 end of DDR. For example, if the total DDR is 16GB, it shrinks to 15.5GB
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| /arch/arm/mach-stm32mp/ |
| A D | tamp_nvram.c | 353 int total = offset + size; in stm32_tamp_nvram_read() local
357 while (i < total) { in stm32_tamp_nvram_read()
359 if (i + sizeof(u32) <= total && IS_ALIGNED(i, sizeof(u32))) { in stm32_tamp_nvram_read()
391 size_t total = offset + size; in stm32_tamp_nvram_write() local
396 while (i < total) { in stm32_tamp_nvram_write()
398 if (i + sizeof(u32) <= total && IS_ALIGNED(i, sizeof(u32))) { in stm32_tamp_nvram_write()
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| /arch/x86/cpu/ |
| A D | mp_init.c | 399 int total = 0; in apic_wait_timeout() local
407 total += 50; in apic_wait_timeout()
408 if (total >= total_delay) { in apic_wait_timeout()
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| /arch/arm/mach-k3/ |
| A D | Kconfig | 49 Describes the total size of the MCU or OCMC MSRAM present on
50 the SoC in use. This doesn't specify the total size of SPL as
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| /arch/x86/cpu/quark/ |
| A D | Kconfig | 132 Note this size must not exceed eSRAM's total size.
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| /arch/mips/mach-octeon/include/mach/ |
| A D | cvmx-pko3.h | 327 u64 total : 16; member
853 hdr_s.s.total = len; in cvmx_pko3_xmit_link_buf()
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| /arch/arm/mach-omap2/ |
| A D | Kconfig | 133 This config option is used to specify the size of the portion of the total
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| /arch/mips/mach-octeon/ |
| A D | cvmx-pko3-compat.c | 364 hdr_s->s.total = pko_command.s.total_bytes; in cvmx_pko3_legacy_xmit()
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| /arch/mips/ |
| A D | Kconfig | 536 The total size of the L1 Dcache, if known at compile time.
548 The total size of the L1 ICache, if known at compile time.
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| /arch/x86/ |
| A D | Kconfig | 579 Sets the total size of the data cache area in memory space. This
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| /arch/arm/include/asm/arch-octeontx2/csrs/ |
| A D | csrs-nix.h | 1296 u64 total : 18; member
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