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Searched refs:tpr0 (Results 1 – 10 of 10) sorted by relevance

/arch/arm/mach-at91/
A Dmpddrc.c60 writel(mpddr_value->tpr0, &mpddr->tpr0); in ddr2_init()
169 writel(mpddr_value->tpr0, &mpddr->tpr0); in ddr3_init()
251 writel(mpddr_value->tpr0, &mpddr->tpr0); in lpddr2_init()
/arch/arm/mach-at91/include/mach/
A Datmel_mpddrc.h17 u32 tpr0; member
34 u32 tpr0; /* 0x0c: Timing Parameter 0 Register */ member
/arch/arm/include/asm/arch-sunxi/
A Ddram_sun4i.h20 u32 tpr0; /* 0x14 dram timing parameters register 0 */ member
79 u32 tpr0; member
A Ddram_sun55i_a523.h125 u32 tpr0; member
A Ddram_sun50i_h616.h156 u32 tpr0; member
A Ddram_sun8i_a23.h28 u32 tpr0; member
/arch/arm/mach-sunxi/
A Ddram_sun8i_a23.c43 .tpr0 = 0x2ab83def,
131 writel((dram_para.tpr0 & 0x000fffff), &mctl_phy->ptr2); in mctl_init()
133 writel((dram_para.tpr0 & 0x3ff00000) >> 2 | in mctl_init()
A Ddram_sun50i_h616.c832 if (para->tpr0 & BIT(30)) in mctl_phy_ca_bit_delay_compensation()
833 val = (para->tpr0 >> 7) & 0x3e; in mctl_phy_ca_bit_delay_compensation()
856 if (para->tpr0 & BIT(31)) { in mctl_phy_ca_bit_delay_compensation()
857 val = (para->tpr0 << 1) & 0x3e; in mctl_phy_ca_bit_delay_compensation()
868 if (para->tpr0 & BIT(31)) { in mctl_phy_ca_bit_delay_compensation()
869 val = (para->tpr0 << 1) & 0x3e; in mctl_phy_ca_bit_delay_compensation()
1335 .tpr0 = CONFIG_DRAM_SUNXI_TPR0,
A Ddram_sun4i.c639 writel(para->tpr0, &dram->tpr0); in dramc_init_helper()
A Ddram_sun55i_a523.c861 val = para->tpr0; in mctl_phy_ca_bit_delay_compensation()
1484 .tpr0 = CONFIG_DRAM_SUNXI_TPR0,

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