1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * From Coreboot soc/intel/broadwell/include/soc/pei_data.h 4 * 5 * Copyright (C) 2014 Google Inc. 6 */ 7 8 #ifndef ASM_ARCH_PEI_DATA_H 9 #define ASM_ARCH_PEI_DATA_H 10 11 #include <linux/linkage.h> 12 13 #define PEI_VERSION 22 14 15 typedef void asmlinkage (*tx_byte_func)(unsigned char byte); 16 17 enum board_type { 18 BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */ 19 BOARD_TYPE_CRB_DESKTOP, /* CRB Desktop */ 20 BOARD_TYPE_USER1, /* SV mobile */ 21 BOARD_TYPE_USER2, /* SV desktop */ 22 BOARD_TYPE_USER3, /* SV server */ 23 BOARD_TYPE_ULT, /* ULT */ 24 BOARD_TYPE_CRB_EMBDEDDED, /* CRB Embedded */ 25 BOARD_TYPE_UNKNOWN, 26 }; 27 28 #define MAX_USB2_PORTS 14 29 #define MAX_USB3_PORTS 6 30 #define USB_OC_PIN_SKIP 8 31 32 enum usb2_port_location { 33 USB_PORT_BACK_PANEL = 0, 34 USB_PORT_FRONT_PANEL, 35 USB_PORT_DOCK, 36 USB_PORT_MINI_PCIE, 37 USB_PORT_FLEX, 38 USB_PORT_INTERNAL, 39 USB_PORT_SKIP, 40 USB_PORT_NGFF_DEVICE_DOWN, 41 }; 42 43 struct usb2_port_setting { 44 /* 45 * Usb Port Length: 46 * [16:4] = length in inches in octal format 47 * [3:0] = decimal point 48 */ 49 uint16_t length; 50 uint8_t enable; 51 uint8_t oc_pin; 52 uint8_t location; 53 } __packed; 54 55 struct usb3_port_setting { 56 uint8_t enable; 57 uint8_t oc_pin; 58 /* 59 * Set to 0 if trace length is > 5 inches 60 * Set to 1 if trace length is <= 5 inches 61 */ 62 uint8_t fixed_eq; 63 } __packed; 64 65 struct pei_data { 66 uint32_t pei_version; 67 68 enum board_type board_type; 69 int boot_mode; 70 int ec_present; 71 int usbdebug; 72 73 /* Base addresses */ 74 uint32_t pciexbar; 75 uint16_t smbusbar; 76 uint32_t xhcibar; 77 uint32_t ehcibar; 78 uint32_t gttbar; 79 uint32_t rcba; 80 uint32_t pmbase; 81 uint32_t gpiobase; 82 uint32_t temp_mmio_base; 83 uint32_t tseg_size; 84 85 /* 86 * 0 = leave channel enabled 87 * 1 = disable dimm 0 on channel 88 * 2 = disable dimm 1 on channel 89 * 3 = disable dimm 0+1 on channel 90 */ 91 int dimm_channel0_disabled; 92 int dimm_channel1_disabled; 93 /* Set to 0 for memory down */ 94 uint8_t spd_addresses[4]; 95 /* Enable 2x Refresh Mode */ 96 int ddr_refresh_2x; 97 /* DQ pins are interleaved on board */ 98 int dq_pins_interleaved; 99 /* Limit DDR3 frequency */ 100 int max_ddr3_freq; 101 /* Disable self refresh */ 102 int disable_self_refresh; 103 /* Disable cmd power/CKEPD */ 104 int disable_cmd_pwr; 105 106 /* USB port configuration */ 107 struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; 108 struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; 109 110 /* 111 * USB3 board specific PHY tuning 112 */ 113 114 /* Valid range: 0x69 - 0x80 */ 115 uint8_t usb3_txout_volt_dn_amp_adj[MAX_USB3_PORTS]; 116 /* Valid range: 0x80 - 0x9c */ 117 uint8_t usb3_txout_imp_sc_volt_amp_adj[MAX_USB3_PORTS]; 118 /* Valid range: 0x39 - 0x80 */ 119 uint8_t usb3_txout_de_emp_adj[MAX_USB3_PORTS]; 120 /* Valid range: 0x3d - 0x4a */ 121 uint8_t usb3_txout_imp_adj_volt_amp[MAX_USB3_PORTS]; 122 123 /* Console output function */ 124 tx_byte_func tx_byte; 125 126 /* 127 * DIMM SPD data for memory down configurations 128 * [CHANNEL][SLOT][SPD] 129 */ 130 uint8_t spd_data[2][2][512]; 131 132 /* 133 * LPDDR3 DQ byte map 134 * [CHANNEL][ITERATION][2] 135 * 136 * Maps which PI clocks are used by what LPDDR DQ Bytes (from CPU side) 137 * DQByteMap[0] - ClkDQByteMap: 138 * - If clock is per rank, program to [0xFF, 0xFF] 139 * - If clock is shared by 2 ranks, program to [0xFF, 0] or [0, 0xFF] 140 * - If clock is shared by 2 ranks but does not go to all bytes, 141 * Entry[i] defines which DQ bytes Group i services 142 * DQByteMap[1] - CmdNDQByteMap: [0] is CmdN/CAA and [1] is CmdN/CAB 143 * DQByteMap[2] - CmdSDQByteMap: [0] is CmdS/CAA and [1] is CmdS/CAB 144 * DQByteMap[3] - CkeDQByteMap : [0] is CKE /CAA and [1] is CKE /CAB 145 * For DDR, DQByteMap[3:1] = [0xFF, 0] 146 * DQByteMap[4] - CtlDQByteMap : Always program to [0xFF, 0] 147 * since we have 1 CTL / rank 148 * DQByteMap[5] - CmdVDQByteMap: Always program to [0xFF, 0] 149 * since we have 1 CA Vref 150 */ 151 uint8_t dq_map[2][6][2]; 152 153 /* 154 * LPDDR3 Map from CPU DQS pins to SDRAM DQS pins 155 * [CHANNEL][MAX_BYTES] 156 */ 157 uint8_t dqs_map[2][8]; 158 159 /* Data read from flash and passed into MRC */ 160 const void *saved_data; 161 int saved_data_size; 162 163 /* Disable use of saved data (can be set by mainboard) */ 164 int disable_saved_data; 165 166 /* Data from MRC that should be saved to flash */ 167 void *data_to_save; 168 int data_to_save_size; 169 struct pei_memory_info meminfo; 170 } __packed; 171 172 void mainboard_fill_pei_data(struct pei_data *pei_data); 173 void broadwell_fill_pei_data(struct pei_data *pei_data); 174 175 #endif 176